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1. WO2017172002 - ELECTROSTATIC DISCHARGE (ESD) ISOLATED INPUT/OUTPUT (I/O) CIRCUITS

Publication Number WO/2017/172002
Publication Date 05.10.2017
International Application No. PCT/US2017/014949
International Filing Date 25.01.2017
Chapter 2 Demand Filed 22.01.2018
IPC
H03K 19/003 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
003Modifications for increasing the reliability
H03K 19/0185 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175Coupling arrangements; Interface arrangements
0185using field-effect transistors only
CPC
H02H 9/046
HELECTRICITY
02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
9Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
04responsive to excess voltage
045adapted to a particular application and not provided for elsewhere
046responsive to excess voltage appearing at terminals of integrated circuits
H03K 19/00315
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
003Modifications for increasing the reliability ; for protection
00315in field-effect transistor circuits
H03K 19/018528
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
0185using field effect transistors only
018507Interface arrangements
018521of complementary type, e.g. CMOS
018528with at least one differential stage
H03K 19/018592
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
0185using field effect transistors only
018592with a bidirectional operation
H03M 9/00
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
9Parallel/series conversion or vice versa
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • WORLEY, Eugene Robert
  • JALILIZEINALI, Reza
  • DUNDIGAL, Sreeker
  • CHEN, Wen-Yi
  • CHILLARA, Krishna Chaitanya
  • KANG, Taeghyun
Agents
  • LENKIN, Alan M.
  • LUTZ, Joseph
  • CROSBY, Cornell D.
  • PARTOW-NAVID, Puya
  • BARZILAY, Ilan N.
  • FASHU-KANU, Alvin V.
Priority Data
15/088,03531.03.2016US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ELECTROSTATIC DISCHARGE (ESD) ISOLATED INPUT/OUTPUT (I/O) CIRCUITS
(FR) CIRCUITS D'ENTRÉE/SORTIE (E/S) ISOLÉS CONTRE LES DÉCHARGES ÉLECTROSTATIQUES (ESD)
Abstract
(EN)
A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal (102) from a pair of I/O transistors of the SERDES differential I/O circuit (120) in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal (104) from the pair of I/O transistors of the SERDES differential I/O circuit (120) in response to the detected electrostatic discharge event.
(FR)
L'invention concerne un procédé de protection d'un circuit d'entrée/sortie (E/S) différentiel de convertisseur parallèle-série.série-parallèle (SERDES) qui comprend la détection d'un événement de décharge électrostatique. Le procédé comprend également la déconnexion sélective d'une borne d'alimentation électrique (102) d'une paire de transistors d'E/S du circuit d'E/S différentiel SERDES (120) en réponse à l'événement de décharge électrostatique détecté. Le procédé comprend en outre la déconnexion sélective d'une borne de masse (104) de la paire de transistors d'E/S du circuit d'E/S différentiel SERDES (120) en réponse à l'événement de décharge électrostatique détecté.
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