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1. (WO2017171843) TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE

Pub. No.:    WO/2017/171843    International Application No.:    PCT/US2016/025597
Publication Date: Fri Oct 06 01:59:59 CEST 2017 International Filing Date: Sat Apr 02 01:59:59 CEST 2016
IPC: H01L 29/78
H01L 21/336
Applicants: INTEL CORPORATION
Inventors: SUNG, Seung Hoon
RACHMADY, Willy
KAVALIEROS, Jack T.
THEN, Han Wui
RADOSAVLJEVIC, Marko
Title: TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE
Abstract:
Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.