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1. (WO2017171716) INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES

Pub. No.:    WO/2017/171716    International Application No.:    PCT/US2016/024555
Publication Date: Fri Oct 06 01:59:59 CEST 2017 International Filing Date: Tue Mar 29 01:59:59 CEST 2016
IPC: H01L 43/02
H01L 43/10
H01L 43/12
Applicants: INTEL CORPORATION
Inventors: WIEGAND, Christopher J.
GOLONZKA, Oleg
RAHMAN, MD Tofizur
DOYLE, Brian S.
DOCZY, Mark L.
O'BRIEN, Kevin P.
OGUZ, Kaan
GHANI, Tahir
SURI, Satyarth
Title: INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES
Abstract:
Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.