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1. (WO2017171716) INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/171716 International Application No.: PCT/US2016/024555
Publication Date: 05.10.2017 International Filing Date: 28.03.2016
IPC:
H01L 43/02 (2006.01) ,H01L 43/10 (2006.01) ,H01L 43/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Details
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
10
Selection of materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
12
Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
WIEGAND, Christopher J.; US
GOLONZKA, Oleg; US
RAHMAN, MD Tofizur; US
DOYLE, Brian S.; US
DOCZY, Mark L.; US
O'BRIEN, Kevin P.; US
OGUZ, Kaan; US
GHANI, Tahir; US
SURI, Satyarth; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES
(FR) PROCÉDÉ DE RECOUVREMENT D'INTERCONNEXION POUR INTÉGRATION DE DISPOSITIFS DE MÉMOIRE VIVE MAGNÉTIQUE ET STRUCTURES RÉSULTANTES
Abstract:
(EN) Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.
(FR) Cette invention concerne des approches pour un procédé de placage d'interconnexion pour intégrer des dispositifs de mémoire vive magnétique (MRAM), et les structures résultantes. Selon un exemple, une structure de mémoire comprend une interconnexion disposée dans une tranchée d'une couche diélectrique au-dessus d'un substrat, l'interconnexion comprenant une couche barrière de diffusion disposée sur un fond et le long de parois latérales de la tranchée jusqu'à une surface supérieure de la couche diélectrique, une couche de remplissage conductrice disposée sur la couche barrière de diffusion et en retrait en dessous de la surface supérieure de la couche diélectrique et d'une surface supérieure de la couche barrière de diffusion, et une couche de recouvrement conductrice disposée sur la couche de remplissage conductrice et entre des parties de paroi latérale de la couche barrière de diffusion. Un élément de mémoire est disposé sur la couche de recouvrement conductrice de l'interconnexion.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)