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1. (WO2017170411) METHOD FOR PROCESSING OBJECT TO BE PROCESSED
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Pub. No.: WO/2017/170411 International Application No.: PCT/JP2017/012407
Publication Date: 05.10.2017 International Filing Date: 27.03.2017
IPC:
H01L 21/3065 (2006.01) ,H05H 1/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H
PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY- CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
1
Generating plasma; Handling plasma
24
Generating plasma
46
using applied electromagnetic fields, e.g. high frequency or microwave energy
Applicants:
東京エレクトロン株式会社 TOKYO ELECTRON LIMITED [JP/JP]; 東京都港区赤坂五丁目3番1号 3-1 Akasaka 5-chome, Minato-ku, Tokyo 1076325, JP
Inventors:
木原 嘉英 KIHARA Yoshihide; JP
久松 亨 HISAMATSU Toru; JP
大石 智之 OISHI Tomoyuki; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
黒木 義樹 KUROKI Yoshiki; JP
柏岡 潤二 KASHIOKA Junji; JP
Priority Data:
2016-06580629.03.2016JP
2016-14747727.07.2016JP
Title (EN) METHOD FOR PROCESSING OBJECT TO BE PROCESSED
(FR) PROCÉDÉ DE TRAITEMENT D'OBJET À TRAITER
(JA) 被処理体を処理する方法
Abstract:
(EN) A wafer W according to an embodiment of the present invention is provided with a layer to be etched EL, an organic film OL, an anti-reflective film AL, and a mask layer MK1, and a method MT according to an embodiment of the present invention is provided with steps in which the mask MK1 is used to perform etching processing on the anti-reflective film AL by plasma within a processing container 12 of a plasma processing device 10 in which the wafer W is accommodated, said plasma being generated within the processing container 12. The following steps are provided: steps ST3a-ST4 in which a protective film SX is conformally formed on the surface of the mask MK1; and steps ST6a-ST7 in which the mask MK1 having the protective film SX formed thereon is used to perform etching of the anti-reflective film AL by removal of the individual atomic layers of the anti-reflective film AL.
(FR) Une tranche W selon un mode de réalisation de la présente invention comporte une couche à graver EL, un film organique OL, un film antireflet AL, et une couche de masque MK1, et un procédé MT selon un mode de réalisation de la présente invention comporte des étapes au cours desquelles le masque MK1 est utilisé pour effectuer un traitement de gravure sur le film antireflet AL par plasma à l'intérieur d'un récipient de traitement 12 d'un dispositif de traitement au plasma 10 dans lequel est reçue la tranche W, ledit plasma étant généré à l'intérieur du récipient de traitement 12. Les étapes suivantes sont mises en œuvre : étapes ST3a-ST4 au cours desquelles un film protecteur SX est formé de manière conforme sur la surface du masque MK1 ; et les étapes ST6a-ST7 au cours desquelles le masque MK1 sur lequel est formé le film protecteur SX est utilisé pour réaliser une gravure du film antireflet AL par élimination des couches atomiques individuelles du film antireflet AL.
(JA) 一実施形態においてウエハWは被エッチング層ELと有機膜OLと反射防止膜ALとマスクMK1とを備え、一実施形態の方法MTは、このウエハWを収容したプラズマ処理装置10の処理容器12内において処理容器12内で発生させたプラズマによりマスクMK1を用いて反射防止膜ALに対しエッチング処理を行う工程を備え、当該工程はマスクMK1の表面に保護膜SXをコンフォーマルに形成する工程ST3a~ST4と、保護膜SXが形成されたマスクMK1を用いて反射防止膜ALを原子層毎に除去することによって反射防止膜ALをエッチングする工程ST6a~ST7とを備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)