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1. WO2017170340 - MEMORY DEVICE

Publication Number WO/2017/170340
Publication Date 05.10.2017
International Application No. PCT/JP2017/012276
International Filing Date 27.03.2017
Chapter 2 Demand Filed 26.09.2017
IPC
G11C 15/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
G06F 12/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G11C 15/02 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
02using magnetic elements
CPC
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G11C 11/4125
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
4125Cells incorporating circuit means for protection against loss of information
G11C 11/419
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
417for memory cells of the field-effect type
419Read-write [R-W] circuits
G11C 15/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
02using magnetic elements
G11C 15/046
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
046using non-volatile storage elements
G11C 2207/2227
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
22Control and timing of internal memory operations
2227Standby or low power modes
Applicants
  • 国立大学法人東北大学 TOHOKU UNIVERSITY [JP]/[JP]
Inventors
  • 馬 奕涛 MA Yitao
  • 遠藤 哲郎 ENDOH Tetsuo
Agents
  • 吉田 正義 YOSHIDA Tadanori
Priority Data
2016-06477728.03.2016JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) MEMORY DEVICE
(FR) DISPOSITIF DE MÉMOIRE
(JA) メモリ装置
Abstract
(EN)
The present invention provides a memory device with which it is possible to promote optimization of power consumption and read out reference data. This memory device 100 is provided with a memory area 113 in which is stored reference data comprising N (≥ 1) dimensions, the one-dimensional space of which comprises M (≥ 1) bits. In the memory area 113, with a discretionary number of memory grains 119 configured from M-bit nonvolatile memory as one unit and a power driver 118 for supplying electric power to the discretionary number of memory grains are provided, as a set, to each area designated by a discretionary number (1 to N) of column lines 117 and M row lines 115. The power driver 118 accepts input of a control signal from the discretionary number of column lines 117, input of a control signal from the M row lines 115, and input of a clock signal, and supplies electric power to a memory grain 119 that constitutes a set with the power driver 118 in synchronism with the clock signal, thereby reading out reference data for each dimension that is stored in the memory grain 119.
(FR)
La présente invention concerne un dispositif de mémoire au moyen duquel il est possible de favoriser l'optimisation de consommation d'énergie et d'extraire des données de référence. Ce dispositif de mémoire (100) comprend une zone de mémoire (113), dans laquelle sont stockées des données de référence comprenant N (≥ 1) dimensions, dont l'espace unidimensionnel comprend M (≥ 1) bits. Dans la zone de mémoire (113), un nombre discrétionnaire de grains de mémoire (119) configurés à partir d'une mémoire non volatile à M bits sous la forme d'une seule unité et un pilote d'alimentation (118) pour fournir de l'énergie électrique au nombre discrétionnaire de grains de mémoire sont fournis, sous la forme d'un ensemble, à chaque zone désignée par un nombre discrétionnaire (1 à N) de lignes de colonne (117) et M lignes de rangée (115). Le pilote d'alimentation (118) accepte l'entrée d'un signal de commande provenant du nombre discrétionnaire de lignes de colonne (117), l'entrée d'un signal de commande provenant des M lignes de rangée (115), et l'entrée d'un signal d'horloge, et fournit de l'énergie électrique à un grain de mémoire (119) qui constitue un ensemble avec le pilote d'alimentation (118) de manière synchrone avec le signal d'horloge, permettant ainsi d'extraire des données de référence pour chaque dimension qui est stockée dans le grain de mémoire (119).
(JA)
消費電力の最適化を図って参照データを読み出すことができるメモリ装置を提供する。メモリ装置100は、N(≧1)次元からなり1次元がM(≧1)ビットからなる参照データが記憶されるメモリ領域113を備え、メモリ領域113において1以上N以下の任意数のコラムライン117とM本のローライン115とにより指定される領域毎に、Mビットの不揮発性メモリを1単位として構成する任意数のメモリグレン119と、任意数のメモリグレンに電力を供給するパワードライバー118とが組として備えられ、パワードライバー118が、任意数のコラムライン117からの制御信号の入力と、M本のローライン115からの制御信号の入力と、クロック信号の入力とを受け、クロック信号に同期して、パワードライバー118と組となるメモリグレン119に電力を供給することにより、当該メモリグレン119に格納されている次元毎の参照データを読み出す。
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