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1. (WO2017169942) MOUNTING DEVICE AND MOUNTING METHOD
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/169942 International Application No.: PCT/JP2017/011081
Publication Date: 05.10.2017 International Filing Date: 21.03.2017
IPC:
H01L 21/60 (2006.01) ,H01L 21/52 (2006.01) ,H05K 13/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
13
Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
04
Mounting of components
Applicants: TORAY ENGINEERING CO., LTD.[JP/JP]; Yaesu Ryumeikan Bldg., 3-22, Yaesu 1-chome, Chuo-ku, Tokyo 1030028, JP
Inventors: MIZUTANI, Yoshihito; JP
ASAHI, Noboru; JP
NIMURA, Masatsugu; JP
Priority Data:
2016-06799030.03.2016JP
Title (EN) MOUNTING DEVICE AND MOUNTING METHOD
(FR) DISPOSITIF DE MONTAGE ET PROCÉDÉ DE MONTAGE
(JA) 実装装置および実装方法
Abstract:
(EN) To provide a mounting device and a mounting method, which do not have adverse effects on semiconductor chips other than one to be bonded by thermal compression when a semiconductor chip that has been temporarily fixed by means of a thermosetting resin is bonded, by thermal compression, to a substrate such as a silicon wafer having a high thermal conductivity. Specifically provided are: a mounting device for bonding a plurality of semiconductor chips, which have been temporarily fixed by means of a thermosetting adhesive, onto a substrate by thermal compression, said mounting device comprising a bonding head that has a press surface that presses a pressurization region which is a region including one or more of semiconductor chips, a bonding stage that supports the pressurization region from the back side of the substrate, and a cooling means that cools semiconductor chips adjacent to the periphery of the pressurization region; and a mounting method.
(FR) L'invention concerne un dispositif de montage et un procédé de montage qui ne présentent pas d'effets indésirables sur des puces en semiconducteur autres que celui de la liaison par compression thermique lorsqu'une puce en semiconducteur, qui a été temporairement fixée au moyen d'une résine thermodurcissable, est liée par compression thermique à un substrat tel qu'une galette en silicium ayant une conductivité thermique élevée. L'invention concerne plus spécifiquement : un dispositif de montage servant à lier, par compression thermique sur un substrat, une pluralité de puces en semiconducteur qui ont été temporairement fixées au moyen d'un adhésif thermodurcissable, ledit dispositif de montage comprenant une tête de liaison qui présente une surface de pressage qui presse une région de mise sous pression, laquelle est une région comprenant une ou plusieurs puces en semiconducteur, une platine de liaison qui supporte la région de mise sous pression depuis le côté arrière du substrat, et un moyen de refroidissement qui refroidit les puces en semiconducteur voisines de la périphérie de la région de mise sous pression. L'invention concerne également un procédé de montage.
(JA) シリコンウェハ等の熱伝導率の高い基板に、熱硬化性樹脂で仮固定された半導体チップを熱圧着するのに際して、熱圧着対象以外の半導体チップに悪影響を及ぼすことのない実装装置および実装方法を提供すること。具体的には、基板上に熱硬化性接着剤を介して仮固定された複数の半導体チップを熱圧着する実装装置であって、1個以上の半導体チップを含む領域を加圧領域として押圧する押圧面とするボンディングヘッドと、前記加圧領域を、前記基板の裏面から支持するボンディングステージと、前記加圧領域の周囲に隣接する半導体チップを冷却する冷却手段とを備えた実装装置および実装方法を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)