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1. (WO2017169173) MOLD AND CIRCUIT DEVICE
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Pub. No.: WO/2017/169173 International Application No.: PCT/JP2017/004931
Publication Date: 05.10.2017 International Filing Date: 10.02.2017
IPC:
B29C 45/27 (2006.01) ,B29C 45/02 (2006.01) ,H01L 21/56 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
29
WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
C
SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
45
Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
17
Component parts, details or accessories; Auxiliary operations
26
Moulds
27
Sprue channels
B PERFORMING OPERATIONS; TRANSPORTING
29
WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
C
SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
45
Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
02
Transfer moulding, i.e. transferring the required volume of moulding material by a plunger from a "shot" cavity into a mould cavity
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
Applicants: KEIHIN CORPORATION[JP/JP]; 26-2, Nishishinjuku 1-chome, Shinjuku-ku, Tokyo 1630539, JP
Inventors: XU, Changlong; JP
Agent: SHIMODA, Yo-ichiro; JP
SHIMODA, Norimasa; JP
SUMIYOSHI, Katsuhiko; JP
TAKIZAWA, Masanori; JP
Priority Data:
2016-06824530.03.2016JP
Title (EN) MOLD AND CIRCUIT DEVICE
(FR) MOULE ET DISPOSITIF DE CIRCUIT
(JA) 金型及び回路装置
Abstract:
(EN) Provided is a mold 10 for transfer molding comprising a lower mold 11 and an upper mold 12. The lower mold 11 and the upper mold 12 are molds that, when clamped to each other, comprise a cavity 13 to mold resin and a gate 21 to supply the resin to the cavity 13. The gate 21 is formed on both sides across a parting surface 14 between the two clamped molds. The gate 21 is formed with plane-symmetry across the parting surface 14, and an upstream part of a flow path connected to the gate 21 is formed in only one of the two molds and is exposed at the parting surface 14.
(FR) La présente invention concerne un moule 10 pour le moulage par transfert comprenant un moule inférieur 11 et un moule supérieur 12. Le moule inférieur 11 et le moule supérieur 12 sont des moules qui, lorsqu'ils sont fixés l'un à l'autre, comprennent une cavité 13 pour mouler de la résine et une grille 21 pour introduire la résine dans la cavité 13. La grille 21 est formée sur les deux côtés d'une surface de séparation 14 entre les deux moules fixés. La grille 21 est formée avec une symétrie plane sur la surface de séparation 14, et une partie en amont d'un trajet d'écoulement relié à la grille 21 est formée dans un seul des deux moules et est exposée au niveau de la surface de séparation 14.
(JA) 下型11と上型12を含んで構成されたトランスファーモールド用の金型10である。下型11と上型12は、互いに型締めされた状態で、樹脂を成形するキャビティ13と、このキャビティ13へ樹脂を供給するゲート21とを有する金型である。ゲート21は、2つの型が型締めされる分割面14を挟んで両側に形成されている。ゲート21は、分割面14を挟んで面対称に形成されており、ゲート21に至る流路の上流部は、2つの型の一方のみに形成されるとともに、分割面14に露出している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)