Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2017166431) TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/166431 International Application No.: PCT/CN2016/084947
Publication Date: 05.10.2017 International Filing Date: 06.06.2016
IPC:
H01L 27/12 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
刘政 LIU, Zheng; CN
Agent:
中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.; 中国北京市 海淀区西三环北路87号4-1105室 Suite 4-1105, No. 87, West 3rd Ring North Rd., Haidian District Beijing 100089, CN
Priority Data:
201610202895.601.04.2016CN
Title (EN) TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE
(FR) SUBSTRAT DE RÉSEAU DE TRANSISTORS À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF D'AFFICHAGE
(ZH) TFT阵列基板及其制造方法、显示装置
Abstract:
(EN) A TFT array substrate and manufacturing method therefor, and a display device comprising the TFT array substrate. The TFT array substrate comprises a substrate base (100) and two thin film transistors located on the substrate base, each thin film transistor comprising an active layer (102, 107) having a source region and a drain region. The two active layers of the two thin film transistors are mutually stacked in the direction perpendicular to the substrate base, and the drain region of one of the two active layers is electrically connected with the source region of the other active layer, so that the two thin film transistors are connected in series. In this way, the present invention can reduce or save the area occupied by each thin film transistor on a base while maintaining a total effective channel length unchanged, thereby facilitating a high resolution design of a display panel.
(FR) Cette invention concerne un substrat de réseau de transistors TFT et son procédé de fabrication, et un dispositif d'affichage comprenant le substrat de réseau de transistors TFT. Le substrat de réseau de transistors TFT comprend une base de substrat (100) et deux transistors à couches minces disposés sur la base de substrat, chaque transistor à couches minces comprenant une couche active (102 107) possédant une région de source et une région de drain. Les deux couches actives des deux transistors à couches minces sont mutuellement empilées dans la direction perpendiculaire à la base de substrat, et la région de drain de l'une des deux couches actives est électriquement connectée à la région de source de l'autre couche active, de sorte que les deux transistors à couches minces sont connectés en série. De cette manière, le substrat selon l'invention permet de réduire ou d'économiser la superficie occupée par chaque transistor à couches minces sur une base tout en maintenant identique une longueur efficace totale de canal, de sorte à faciliter une conception à haute résolution d'un panneau d'affichage.
(ZH) 一种TFT阵列基板及其制造方法,以及包括该TFT阵列基板的显示装置。该TFT阵列基板包括衬底基板(100)和位于衬底基板上的两个薄膜晶体管,每个薄膜晶体管包括具有源区和漏区的有源层(102、107),两个薄膜晶体管的两个有源层在垂直于衬底基板的方向上相互叠置,且两个有源层中的一个有源层的漏区与另一个有源层的源区电连接,使得两个薄膜晶体管串联连接,由此能够在保持总的有效沟道长度不变的同时,减小或节省每个薄膜晶体管在基板上所占的面积,有利于显示面板的高分辨率设计。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)