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1. (WO2017157110) METHOD OF CONTROLLING HIGH-SPEED ACCESS TO DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY, AND DEVICE

Pub. No.:    WO/2017/157110    International Application No.:    PCT/CN2017/072862
Publication Date: Fri Sep 22 01:59:59 CEST 2017 International Filing Date: Sat Feb 04 00:59:59 CET 2017
IPC: G11C 7/00
Applicants: SANECHIPS TECHNOLOGY CO., LTD.
深圳市中兴微电子技术有限公司
Inventors: YUE, Leiting
岳雷霆
Title: METHOD OF CONTROLLING HIGH-SPEED ACCESS TO DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY, AND DEVICE
Abstract:
A method of controlling high-speed access to a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and a device. The method comprises: dividing, according to a dynamic allocation strategy, a DDR SDRAM into variable buffer blocks (101); and during a read or write operation with respect to the variable buffer blocks, scheduling, according to a weighted round robin strategy, a read/write operation with respect to a plurality of channels, and balancing read/write bandwidth (102).