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1. (WO2017156877) ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/156877 International Application No.: PCT/CN2016/083644
Publication Date: 21.09.2017 International Filing Date: 27.05.2016
IPC:
H01L 21/768 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
北京京东方显示技术有限公司 BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国北京市 经济技术开发区经海一路118号 No. 118 Jinghaiyilu, BDA Beijing 100176, CN
Inventors:
任锦宇 REN, Jinyu; CN
王丹 WANG, Dan; CN
徐长健 XU, Changjian; CN
马国靖 MA, Guojing; CN
周波 ZHOU, Bo; CN
Agent:
北京银龙知识产权代理有限公司 DRAGON INTELLECTUAL PROPERTY LAW FIRM; 中国北京市 海淀区西直门北大街32号枫蓝国际中心2号楼10层 10F, Bldg.2, Maples International Center No.32 Xizhimen North Street, Haidian District Beijing 100082, CN
Priority Data:
201610143214.314.03.2016CN
Title (EN) ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
(FR) SUBSTRAT DE RÉSEAU ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF D'AFFICHAGE
(ZH) 阵列基板及其制作方法、显示装置
Abstract:
(EN) An array substrate and method for manufacturing same, and a display device. The array substrate comprises a first conductive pattern (2), an insulation layer (3/5) covering the first conductive pattern, and a second conductive pattern (8) located on the insulation layer. The insulation layer comprises a via hole (9) used for connecting the first conductive pattern to the second conductive pattern; a conductive post (10) connected to the first conductive pattern and the second conductive pattern is formed in the via hole.
(FR) L'invention concerne un substrat de réseau et son procédé de fabrication, et un dispositif d'affichage. Le substrat de réseau comprend un premier motif conducteur (2), une couche d'isolation (3/5) recouvrant le premier motif conducteur, et un second motif conducteur (8) situé sur la couche d'isolation. La couche d'isolation comprend un trou d'interconnexion (9) utilisé pour connecter le premier motif conducteur au second motif conducteur ; une tige conductrice (10) connectée au premier motif conducteur et au second motif conducteur est formée dans le trou d'interconnexion.
(ZH) 一种阵列基板及其制作方法、显示装置。阵列基板包括第一导电图形(2)、覆盖该第一导电图形的绝缘层(3/5)、位于该绝缘层上的第二导电图形(8),该绝缘层包括有用以连接该第一导电图形和该第二导电图形的过孔(9),该过孔内形成有与该第一导电图形和第二导电图形连接的导电柱(10)。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)