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1. (WO2017155662) MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY SYSTEM

Pub. No.:    WO/2017/155662    International Application No.:    PCT/US2017/017191
Publication Date: Fri Sep 15 01:59:59 CEST 2017 International Filing Date: Fri Feb 10 00:59:59 CET 2017
IPC: G06F 12/02
G06F 13/16
G11C 7/10
G06F 12/10
G06F 12/1081
G06F 12/08
G06F 12/06
Applicants: QUALCOMM INCORPORATED
Inventors: CHUN, Dexter Tamio
LI, Yanru
JAFFARI, Javid
ANSARI, Amin
Title: MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY SYSTEM
Abstract:
Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access region in a first memory rank and a dedicated parallel access region in a second memory rank. A request is received for a virtual memory page. If the request comprises a performance hint, the virtual memory page is selectively assigned to a free physical page in the dedicated serial access in the first memory rank and the dedicated parallel access region in the second memory rank.