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|1. (WO2017155662) MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY SYSTEM|
|Inventors:||CHUN, Dexter Tamio
|Title:||MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY SYSTEM|
Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access region in a first memory rank and a dedicated parallel access region in a second memory rank. A request is received for a virtual memory page. If the request comprises a performance hint, the virtual memory page is selectively assigned to a free physical page in the dedicated serial access in the first memory rank and the dedicated parallel access region in the second memory rank.