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1. (WO2017155615) METHODS AND APPARATUS TO IMPROVE COMPUTING RESOURCE UTILIZATION
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Pub. No.: WO/2017/155615 International Application No.: PCT/US2017/014382
Publication Date: 14.09.2017 International Filing Date: 20.01.2017
IPC:
G06F 9/50 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
50
Allocation of resources, e.g. of the central processing unit (CPU)
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PALERMO, Stephen Thomas; US
KAMHOUT, Dwarkadisha D.; US
GANESH, Pradeepsunder; US
GUPTA, Prabhat K.; US
Agent:
CESARZ, Peter J.; US
Priority Data:
15/087,28731.03.2016US
62/306,04809.03.2016US
Title (EN) METHODS AND APPARATUS TO IMPROVE COMPUTING RESOURCE UTILIZATION
(FR) PROCÉDÉS ET APPAREIL POUR AMÉLIORER L’UTILISATION DE RESSOURCES DE CALCUL
Abstract:
(EN) Methods, apparatus, systems and articles of manufacture are disclosed to improve computing resource utilization. An example apparatus includes an application specific sensor (AS) to monitor a workload of a platform, the workload executing on at least one general purpose central processing unit (CPU) of the platform, and a dynamic deployment module (DDM) to: in response to a workload performance threshold being satisfied, identify a bit stream capable of configuring a field programmable gate array (FPGA) to execute the workload, and configure the FPGA via the bit stream to execute at least a portion of the workload.
(FR) L’invention concerne des procédés, un appareil, des systèmes et des articles de fabrication pour améliorer l’utilisation de ressources de calcul. Un appareil illustratif inclut un capteur spécifique à une application (AS) pour contrôler une charge utile d’une plateforme, la charge utile étant exécutée sur au moins une unité centrale de traitement (UCT) d’usage général de la plateforme, et un module de déploiement dynamique (DDM) pour : en réponse à la satisfaction à un seuil de performance de charge utile, identifier un flux binaire pouvant configurer une matrice prédiffusée programmable par l’utilisateur (FPGA) pour exécuter la charge utile, et configurer la FPGA par le biais du flux binaire pour exécuter au moins une partie de la charge utile.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)