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1. (WO2017155508) APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/155508 International Application No.: PCT/US2016/021243
Publication Date: 14.09.2017 International Filing Date: 07.03.2016
IPC:
H01L 43/02 (2006.01) ,H01L 43/08 (2006.01) ,H01L 43/10 (2006.01) ,H01L 43/12 (2006.01) ,G11C 11/16 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Details
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
08
Magnetic-field-controlled resistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
10
Selection of materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
43
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
12
Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02
using magnetic elements
16
using elements in which the storage effect is based on magnetic spin effect
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
LEE, Kevin J.; US
GOLONZKA, Oleg; US
GHANI, Tahir; US
BRAIN, Ruth A.; US
WANG, Yih; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
(FR) APPROCHES POUR INTÉGRER DES MATRICES MÉMOIRE STT-MRAM DANS UN PROCESSEUR LOGIQUE, ET STRUCTURES AINSI OBTENUES
Abstract:
(EN) Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.
(FR) L'invention porte sur des approches pour intégrer des matrices de mémoire vive magnétique à couple de transfert de spin (STT-MRAM) dans un processeur logique, et sur les structures ainsi obtenues. Dans un exemple, un processeur logique comprend une région logique comprenant des appariements ligne métallique/trou d'interconnexion disposés dans une couche diélectrique disposée au-dessus d'un substrat. Le processeur logique comprend également une matrice mémoire vive magnétique à couple de transfert de spin (STT-MRAM) comprenant une pluralité de jonctions tunnel magnétique (MTJ). Les MTJ sont disposées dans la couche diélectrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)