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1. (WO2017155507) APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES

Pub. No.:    WO/2017/155507    International Application No.:    PCT/US2016/021241
Publication Date: Fri Sep 15 01:59:59 CEST 2017 International Filing Date: Tue Mar 08 00:59:59 CET 2016
IPC: H01L 43/02
H01L 43/08
H01L 43/10
H01L 43/12
Applicants: INTEL CORPORATION
Inventors: LEE, Kevin J.
WANG, Yih
Title: APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
Abstract:
Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.