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1. (WO2017155155) BIDIRECTIONAL CONDUCTIVE SOCKET FOR TESTING SEMICONDUCTOR DEVICE, BIDIRECTIONAL CONDUCTIVE MODULE FOR TESTING SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/155155 International Application No.: PCT/KR2016/004887
Publication Date: 14.09.2017 International Filing Date: 10.05.2016
IPC:
G01R 31/26 (2014.01) ,G01R 1/04 (2006.01) ,G01R 1/067 (2006.01) ,G01R 1/073 (2006.01) ,G01R 3/00 (2006.01)
[IPC code unknown for G01R 31/26][IPC code unknown for G01R 1/04][IPC code unknown for G01R 1/067][IPC code unknown for G01R 1/073][IPC code unknown for G01R 3]
Applicants:
주식회사 이노글로벌 INNO GLOBAL INC. [KR/KR]; 광주시 북구 첨단과기로 123 123 Cheomdangwagi-ro Buk-gu Gwangju 61005, KR
Inventors:
이은주 LEE, Eun jou; KR
김근택 KIM, Geun taek; KR
Agent:
특허법인 남촌 NAMCHON INTERNATIONAL PATENT AND LAW FIRM; 광주시 북구 첨단과기로 313, A동 104호 한국산업단지공단(대촌동) (Daechon-dong) A-104 Korea Industrial Complex Corp. 313, Cheomdangwagi-ro Buk-gu Gwangju 61008, KR
Priority Data:
10-2016-002686607.03.2016KR
10-2016-004324108.04.2016KR
Title (EN) BIDIRECTIONAL CONDUCTIVE SOCKET FOR TESTING SEMICONDUCTOR DEVICE, BIDIRECTIONAL CONDUCTIVE MODULE FOR TESTING SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR
(FR) DOUILLE CONDUCTRICE BIDIRECTIONNELLE POUR TEST DE DISPOSITIF SEMI-CONDUCTEUR, MODULE CONDUCTEUR BIDIRECTIONNEL POUR TEST DE DISPOSITIF SEMI-CONDUCTEUR, ET PROCÉDÉ DE FABRICATION ASSOCIÉ
(KO) 반도체 디바이스 테스트용 양방향 도전성 소켓, 반도체 디바이스 테스트용 양방향 도전성 모듈 및 이의 제조방법
Abstract:
(EN) A bidirectional conductive module for testing a semiconductor device, according to one embodiment of the present invention, comprises: a substrate part having a structure bent such that one surface thereof faces the semiconductor device and another surface thereof faces an inspection circuit board; a plurality of terminal pins having a plurality of first conductive patterns linearly spaced apart from each other at a first pitch interval on the one surface of the substrate part so as to be electrically connected to respective terminals of the semiconductor device, and a plurality of second conductive patterns linearly spaced apart from each other at a second pitch interval greater than the first pitch interval on the other surface of the substrate part so as to be electrically connected to respective terminals of the inspection circuit board; and an elastic support part connected to the substrate part so as to elastically support the substrate part, wherein it is preferable for the plurality of terminal pins to be provided on the substrate part such that the plurality of first conductive patterns are arranged linearly while being spaced apart at the first pitch interval on the one surface of the substrate part, and the plurality of second conductive patterns are arranged in a zigzag form by being misaligned at the second pitch interval on the other surface of the substrate part, and thus the plurality of first conductive patterns come in contact with the terminals of the semiconductor device at the first pitch interval, and the plurality of second conductive patterns come in contact with the terminals of the inspection circuit board at the second pitch interval, such that the terminals of the semiconductor device and the terminals of the inspection circuit board are electrically connected.
(FR) Un module conducteur bidirectionnel pour tester un dispositif semi-conducteur, selon un mode de réalisation de la présente invention, comprend : une partie de substrat ayant une structure courbée de telle sorte qu'une surface de cette dernière fait face au dispositif semi-conducteur et une autre surface de cette dernière fait face à une carte de circuit d'inspection ; une pluralité de broches de borne ayant une pluralité de premiers motifs conducteurs espacés linéairement les uns des autres selon un premier intervalle de pas sur ladite une surface de la partie de substrat de manière à être électriquement connectés à des bornes respectives du dispositif semi-conducteur, et une pluralité de seconds motifs conducteurs espacés linéairement les uns des autres selon un second intervalle de pas supérieur au premier intervalle de pas sur l'autre surface de la partie de substrat de manière à être électriquement connectés à des bornes respectives de la carte de circuit d'inspection ; et une partie de support élastique reliée à la partie de substrat de manière à porter élastiquement la partie de substrat ; il est préférable pour la pluralité de broches de borne d'être disposée sur la partie de substrat de telle sorte que la pluralité de premiers motifs conducteurs sont agencés linéairement en étant espacée les uns des autres selon le premier intervalle de pas sur ladite une surface de la partie de substrat, et la pluralité de seconds motifs conducteurs sont agencés en forme de zigzag en étant désalignés selon le second intervalle de pas sur l'autre surface de la partie de substrat, et ainsi la pluralité de premiers motifs conducteurs entre en contact avec les bornes du dispositif semi-conducteur selon le premier intervalle de pas, et la pluralité de seconds motifs conducteurs entre en contact avec les bornes de la carte de circuit d'inspection selon le second intervalle de pas, de telle sorte que les bornes du dispositif semi-conducteur et les bornes de la carte de circuit d'inspection sont électriquement connectées.
(KO) 본 발명의 일 실시예에 따른 반도체 디바이스 테스트용 양방향 도전성 모듈은 일면이 반도체소자를 향하고 다른 일면이 검사회로기판을 향하도록 절곡된 구조를 가진 기판부; 기판부의 일면에서 상호 간에 제 1 피치간격으로 일렬로 이격되어 반도체소자의 단자에 각각 전기적으로 연결되는 복수의 제 1 도전성패턴과, 기판부의 다른 일면에서 상호 간에 제 1 피치간격보다 큰 제 2 피치간격으로 일렬로 이격되어 검사회로기판의 단자에 각각 전기적으로 연결되는 복수의 제 2 도전성패턴이 마련된 복수의 단자핀; 및 기판부를 탄성지지토록 기판부에 연결된 탄성지지부를 포함하고, 복수의 단자핀은 기판부의 일면에서 복수의 제 1 도전성패턴이 제 1 피치간격만큼 이격되어 일렬로 배열되고, 기판부의 다른 일면에서 복수의 제 2 도전성패턴이 제 2 피치간격만큼 어긋나게 배치되어 지그재그형태로 배열되도록 기판부에 마련되어, 복수의 제 1 도전성패턴이 반도체소자의 단자에 대해 제 1 피치간격으로 접촉되고, 복수의 제 2 도전성패턴이 검사회로기판의 단자에 대해 제 2 피치간격으로 접촉되어, 반도체소자의 단자와 검사회로기판의 단자를 전기적으로 연결하는 것이 바람직하다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)