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1. (WO2017154167) MULTILAYER LAMINATE PLATE AND PRODUCTION METHOD FOR MULTILAYERED PRINTED WIRING BOARD USING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/154167 International Application No.: PCT/JP2016/057563
Publication Date: 14.09.2017 International Filing Date: 10.03.2016
IPC:
H05K 3/46 (2006.01) ,B32B 7/02 (2006.01) ,B32B 15/08 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
7
Layered products characterised by the relation between layers, i.e. products essentially comprising layers having different physical properties or products characterised by the interconnection of layers
02
in respect of physical properties, e.g. hardness
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
15
Layered products essentially comprising metal
04
comprising metal as the main or only constituent of a layer, next to another layer of a specific substance
08
of synthetic resin
Applicants:
三井金属鉱業株式会社 MITSUI MINING & SMELTING CO., LTD. [JP/JP]; 東京都品川区大崎一丁目11番1号 1-11-1 Osaki, Shinagawa-ku, Tokyo 1418584, JP
Inventors:
米田 祥浩 YONEDA, Yoshihiro; JP
Agent:
特許業務法人翔和国際特許事務所 SHOWA INTERNATIONAL PATENT FIRM; 東京都港区赤坂二丁目5番7号NIKKEN赤坂ビル7階 NIKKEN AKASAKA BLDG., 7F., 5-7, Akasaka 2-chome, Minato-Ku, Tokyo 1070052, JP
Priority Data:
Title (EN) MULTILAYER LAMINATE PLATE AND PRODUCTION METHOD FOR MULTILAYERED PRINTED WIRING BOARD USING SAME
(FR) PLAQUE DE LAMINAT MULTICOUCHE ET PROCÉDÉ DE PRODUCTION DE CÂBLAGE IMPRIMÉ MULTICOUCHE L’UTILISANT
(JA) 多層積層板及びこれを用いた多層プリント配線板の製造方法
Abstract:
(EN) This multilayer laminate plate (10) comprise: a middle conductive layer (11a); a first dielectric layer (12a) and a second dielectric layer (12b), each disposed directly on each surface of the middle conductive layer (11a); a first external surface conductive layer (13a) disposed directly on the outer side of the first dielectric layer (12a); and a second external surface conductive layer (13b) directly disposed on the outer side of the second dielectric layer (12b). The first external surface conductive layer (13a) and the second external surface conductive layer (13b) constitute the external surfaces of the multilayer laminate plate (10). The middle conductive layer (11a) is formed in an uninterrupted state over the entire region in the in-plane direction of the multilayer laminate plate (10). The variations in the thickness of the first dielectric layer (12a) and the variations in the thickness of the second dielectric layer (12b) are each independently 15% or less.
(FR) La présente invention concerne une plaque de laminat multicouche (10) qui comprend : une couche conductrice intermédiaire (11a) ; une première couche diélectrique (12a) et une seconde couche diélectrique (12b), disposées chacune directement sur chaque surface de la couche conductrice intermédiaire (11a) ; une première couche conductrice de surface externe (13a) disposée directement sur le côté externe de la première couche diélectrique (12a) ; et une seconde couche conductrice de surface externe (13b) directement disposée sur le côté externe de la seconde couche diélectrique (12b). La première couche conductrice de surface externe (13a) et la seconde couche conductrice de surface externe (13b) constituent les surfaces externes de la plaque de laminat multicouche (10). La couche conductrice intermédiaire (11a) est formée dans un état non interrompu sur la région entière dans la direction dans le plan de la plaque de laminat multicouche (10). Les variations de l’épaisseur de la première couche diélectrique (12a) et les variations de l’épaisseur de la seconde couche diélectrique (12b) sont chacune indépendamment de 15 % ou moins.
(JA) 多層積層板(10)は、中央導電層(11a)と、その各面に直接配置された第1誘電体層(12a)及び第2誘電体層(12b)と、第1誘電体層(12a)の外側に直接配置された第1外面導電層(13a)と、第2誘電体層(12b)の外側に直接配置された第2外面導電層(13b)とを備える。第1外面導電層(13a)及び第2外面導電層(13b)が、多層積層板(10)の外面をなす。中央導電層(11a)は、多層積層板(10)の面内方向の全域にわたり、べた状態で形成されている。第1誘電体層(12a)の厚みのばらつき及び第2誘電体層(12b)の厚みのばらつきが、それぞれ独立に15%以下である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)