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1. (WO2017153860) CHARGE SHARING CIRCUIT
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Pub. No.: WO/2017/153860 International Application No.: PCT/IB2017/051080
Publication Date: 14.09.2017 International Filing Date: 24.02.2017
IPC:
H03M 1/10 (2006.01) ,H02M 3/07 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
1
Analogue/digital conversion; Digital/analogue conversion
10
Calibration or testing
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
M
APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
3
Conversion of dc power input into dc power output
02
without intermediate conversion into ac
04
by static converters
06
using resistors or capacitors, e.g. potential divider
07
using capacitors charged and discharged alternately by semiconductor devices with control electrode
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, NY 10504, US
IBM (CHINA) INVESTMENT COMPANY LTD. [CN/CN]; 25/F, Pangu Plaza, No. 27, Central North 4th Ring Road, Chaoyang District Beijing 100101, CN (MG)
IBM RESEARCH GMBH [CH/CH]; IBM Research - Zurich Saeumerstrasse 4 8803 Rueschlikon, CH (MG)
Inventors:
KULL, Lukas; CH
LUU, Danny Chen-Hsien; CH
Agent:
KLETT, Peter; DE
Priority Data:
15/064,33108.03.2016US
Title (EN) CHARGE SHARING CIRCUIT
(FR) CIRCUIT DE PARTAGE DE CHARGE
Abstract:
(EN) A charge sharing circuit for generating a calibration voltage. The circuit comprises a calibration capacitor for providing at an upper terminal of the calibration capacitor the calibration voltage. The circuit further comprises a series connection of a plurality of N switches, wherein N is an integer > 2, and a plurality of at least N-1 switching capacitors. Each switching capacitor is coupled to one connecting node connecting two of the N switches. One side of the series connection of the plurality of N switches is coupled to the upper terminal of the calibration capacitor and the other side of the series connection of the N switches is coupled to a fixed voltage. The circuit is configured to transmit at least two clock signals to selectively drive at least two distinct subsets of the switches. There is further provided a corresponding method and a corresponding design structure.
(FR) L'invention concerne un circuit de partage de charge pour générer une tension d'étalonnage. Le circuit comprend un condensateur d'étalonnage pour fournir la tension d'étalonnage au niveau d'une borne supérieure du condensateur d'étalonnage. Le circuit comprend en outre une connexion en série d'une pluralité de N commutateurs, N étant un entier > 2, et une pluralité d'au moins N-1 condensateurs de commutation. Chaque condensateur de commutation est accouplé à un nœud de connexion reliant deux des N commutateurs. Un côté de la connexion en série de la pluralité de N commutateurs est accouplé à la borne supérieure du condensateur d'étalonnage et l'autre côté de la connexion en série des N commutateurs est accouplé à une tension fixe. Le circuit est configuré pour transmettre au moins deux signaux d'horloge pour commander sélectivement au moins deux sous-ensembles distincts des commutateurs. L'invention concerne en outre un procédé correspondant et une structure de conception correspondante.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)