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1. (WO2017153852) CIRCUIT, APPARATUS, DIGITAL PHASE LOCKED LOOP, RECEIVER, TRANSCEIVER, MOBILE DEVICE, METHOD AND COMPUTER PROGRAM TO REDUCE NOISE IN A PHASE SIGNAL
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Pub. No.: WO/2017/153852 International Application No.: PCT/IB2017/050361
Publication Date: 14.09.2017 International Filing Date: 24.01.2017
IPC:
H03H 11/12 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
H
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
11
Networks using active elements
02
Multiple-port networks
04
Frequency selective two-port networks
12
using amplifiers with feedback
Applicants:
INTEL IP CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, CA 95054, US
Inventors:
BANIN, Elan; IL
MAROM, Tamar; IL
HOROVITZ, Gil; IL
BANIN, Rotem; IL
Agent:
ARABI, Mani; c/o 2SPL PATENTANWÄLTE PARTG MBB P.O. Box 151723 80050 Muenchen, DE
Priority Data:
16159964.211.03.2016EP
Title (EN) CIRCUIT, APPARATUS, DIGITAL PHASE LOCKED LOOP, RECEIVER, TRANSCEIVER, MOBILE DEVICE, METHOD AND COMPUTER PROGRAM TO REDUCE NOISE IN A PHASE SIGNAL
(FR) CIRCUIT, APPAREIL, BOUCLE À PHASE NUMÉRIQUE VERROUILLÉE, RÉCEPTEUR, ÉMETTEUR-RÉCEPTEUR, DISPOSITIF MOBILE, PROCÉDÉ ET PROGRAMME D'ORDINATEUR POUR RÉDUIRE LE BRUIT DANS UN SIGNAL DE PHASE
Abstract:
(EN) A circuit (10) is configured to reduce a noise component of a measured phase signal. The circuit (10) comprises an input (12) for a phase signal of an oscillator and an error signal estimator (14) configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit (20) further comprises a combiner (16) configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.
(FR) L'invention concerne un circuit (10) qui est configuré pour réduire une composante de bruit d'un signal de phase mesuré. Le circuit (10) comprend une entrée (12) pour un signal de phase d'un oscillateur et un dispositif d'estimation de signal d'erreur (14) configuré pour déterminer des informations de parité et une amplitude d'erreur estimée dans le signal de phase sur la base des informations de parité. Le circuit (20) comprend en outre un dispositif de combinaison (16) configuré pour fournir le signal de phase mesuré ayant la composante de bruit réduite sur la base d'une combinaison du signal de phase et de l'amplitude d'erreur estimée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)