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1. (WO2017153244) OPTOELECTRONIC MULTI-CHIP SEMICONDUCTOR COMPONENT
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Pub. No.: WO/2017/153244 International Application No.: PCT/EP2017/054893
Publication Date: 14.09.2017 International Filing Date: 02.03.2017
IPC:
H01L 25/075 (2006.01) ,H01L 33/62 (2010.01) ,H01L 33/46 (2010.01) ,H01L 33/48 (2010.01) ,H01L 33/60 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
075
the devices being of a type provided for in group H01L33/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
62
Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
44
characterised by the coatings, e.g. passivation layer or anti-reflective coating
46
Reflective coating, e.g. dielectric Bragg reflector
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
58
Optical field-shaping elements
60
Reflective elements
Applicants:
OSRAM OPTO SEMICONDUCTORS GMBH [DE/DE]; Leibnizstr. 4 93055 Regensburg, DE
Inventors:
HERRMANN, Siegfried; DE
Agent:
EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHAFT MBH; Schloßschmidstr. 5 80639 München, DE
Priority Data:
10 2016 104 202.108.03.2016DE
Title (EN) OPTOELECTRONIC MULTI-CHIP SEMICONDUCTOR COMPONENT
(FR) COMPOSANT SEMI-CONDUCTEUR OPTOÉLECTRONIQUE À MULTIPLES PUCES
(DE) OPTOELEKTRONISCHES MULTI-CHIP HALBLEITERBAUTEIL
Abstract:
(EN) The optoelectronic semiconductor component (1) comprises a housing (2) having a cutout (20), and also a first semiconductor chip (31) for generating light of a first colour and a second semiconductor chip (32) for generating light of a second colour, wherein the second colour is different from the first colour. During operation, a mixed radiation comprising at least light of the first colour is emitted along a main emission direction (M). The first semiconductor chip (31) is arranged in a first plane (P1) and the second semiconductor chip (32) is arranged in a second plane (P2) in the cutout (20), wherein the two planes (P1, P2) succeed one another along the main emission direction (M). Active zones (33) of the semiconductor chips (31, 32) are arranged alongside one another as seen in plan view parallel to the main emission direction (M). At least 20% of the cutout is filled by the semiconductor chips (31, 32), as seen in plan view. An electrical connection area (61) of the first semiconductor chip (31) forms a part of a mounting area (22) of the semiconductor component (1).
(FR) L'invention concerne un composant semi-conducteur optoélectronique (1) qui comprend un boîtier (2) doté d’un évidement (20) ainsi qu’une première puce semi-conductrice (31) servant à produire une lumière d’une première couleur et une seconde puce (32) servant à produire une lumière d’une seconde couleur, la seconde couleur étant différente de la première couleur. En service, un rayonnement mixte, comportant au moins la lumière de la première couleur, est émis le long d’une direction principale de rayonnement (M). La première puce semi-conductrice (31) est disposée dans un premier plan (P1) tandis que la seconde puce semi-conductrice (32) est disposée dans un second plan (P2) dans l’évidement (20), les deux plans (P1, P2) se suivant le long de la direction principale de rayonnement (M). Sur une vue de dessus parallèlement à la direction principale de rayonnement (M), des zones actives (33) des puces semi-conductrices (31, 32) sont disposées les unes à côté des autres. L’évidement est, vu de dessus, rempli au moins à 20 % par les puces semi-conductrices (31, 32). Une surface de branchement électrique (61) de la première puce semi-conductrice (31) forme une partie d’une surface de montage (22) du composant semi-conducteur (1).
(DE) Es umfasst das optoelektronische Halbleiterbauteil (1) ein Gehäuse (2) mit einer Ausnehmung (20) sowie einen ersten Halbleiterchip (31) zur Erzeugung von Licht einer ersten Farbe und einen zweiten Halbleiterchip (32) zur Erzeugung von Licht einer zweiten Farbe, wobei die zweite Farbe von der ersten Farbe verschieden ist. Im Betrieb wird entlang einer Hauptabstrahlrichtung (M) eine Mischstrahlung, umfassend zumindest Licht der ersten Farbe, emittiert. Der erste Halbleiterchip (31) ist in einer ersten Ebene (P1) und der zweite Halbleiterchip (32) in einer zweiten Ebene (P2) in der Ausnehmung (20) angeordnet, wobei die beiden Ebenen (P1, P2) entlang der Hauptabstrahlrichtung (M) aufeinander folgen. In Draufsicht parallel zur Hauptabstrahlrichtung (M) gesehen sind aktive Zonen (33) der Halbleiterchips (31, 32) nebeneinander angeordnet. Die Ausnehmung ist, in Draufsicht gesehen, zu mindestens 20 % von den Halbleiterchips (31, 32) ausgefüllt. Eine elektrische Anschlussfläche (61) des ersten Halbleiterchips (31) bildet einen Teil einer Montagefläche (22) des Halbleiterbauteils (1).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)