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1. (WO2017152552) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/152552 International Application No.: PCT/CN2016/088071
Publication Date: 14.09.2017 International Filing Date: 01.07.2016
IPC:
H01L 21/336 (2006.01) ,H01L 21/311 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No. 10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
北京京东方显示技术有限公司 BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国北京市 北京经济技术开发区经海一路118号 No. 118 Jinghaiyilu, BDA Beijing 100176, CN
Inventors:
郭会斌 GUO, Huibin; CN
张小祥 ZHANG, Xiaoxiang; CN
王静 WANG, Jing; CN
Agent:
北京天昊联合知识产权代理有限公司 TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; 中国北京市 东城区建国门内大街28号民生金融中心D座10层陈源 Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201610133484.609.03.2016CN
Title (EN) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
(FR) TRANSISTOR EN COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION, SUBSTRAT DE MATRICE ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF D'AFFICHAGE
(ZH) 薄膜晶体管及制造方法、阵列基板及制造方法、显示装置
Abstract:
(EN) Provided are a thin film transistor and a method for manufacturing same, an array substrate and a method for manufacturing same, and a display device. The method for manufacturing a thin film transistor comprises: forming a protective layer (501) between source and drain electrodes to be formed on an active layer (400); forming source and drain metallic layers (600) on the active layer (400) having the protective layer (501); coating the source and drain metallic layers (600) with a photoresist; forming a photoresist reserved region (602) and a photoresist unreserved region (601), wherein the photoresist reserved region (602) corresponds to a region of the source and drain electrodes to be formed and the photoresist unreserved region (601) corresponds to the remaining region; etching the source and drain metallic layers (600) corresponding to the photoresist unreserved region (601) to form source and drain electrodes, and exposing the protective layer (501) on the active layer (400); and removing the photoresist and the protective layer (501) on the source and drain electrodes.
(FR) L'invention concerne un transistor en couches minces et son procédé de fabrication, un substrat de matrice et son procédé de fabrication, et un dispositif d'affichage. Le procédé de fabrication d'un transistor en couches minces comprend : former une couche protectrice (501) entre des électrodes de source et de drain à former sur une couche active (400) ; former des couches métalliques de source et de drain (600) sur la couche active (400) comportant la couche protectrice (501) ; recouvrir les couches métalliques de source et de drain (600) d'une résine photosensible ; former une région de réserve de résine photosensible (602) et une région hors réserve de résine photosensible (601), la région de réserve de résine photosensible (602) correspondant à une région des électrodes de source et de drain à former et la région hors réserve de résine photosensible (601) correspondant à la région restante ; graver les couches métalliques de source et de drain (600) correspondant à la région hors réserve de résine photosensible (601) de façon à former des électrodes de source et de drain, et exposer la couche protectrice (501) sur la couche active (400) ; et éliminer la résine photosensible et la couche protectrice (501) sur les électrodes de source et de drain.
(ZH) 提供了薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置。所述制造薄膜晶体管的方法包括:在有源层(400)上方待形成的源漏电极之间的区域形成保护层(501),在形成有保护层(501)的有源层(400)上方形成源漏金属层(600),在所述源漏金属层(600)上涂覆光刻胶,以及形成光刻胶保留区域(602)和光刻胶不保留区域(601),其中所述光刻胶保留区域(602)对应于待形成的源漏电极的区域,所述光刻胶不保留区域(601)对应于其他区域;刻蚀掉与所述光刻胶不保留区域(601)对应的源漏金属层(600),以形成源漏电极,并且露出所述有源层(400)上方的所述保护层(501);以及去除所述源漏电极上方的光刻胶和所述保护层(501)。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)