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1. (WO2017152191) MOSFET TRANSISTORS WITH ROBUST SUBTHRESHOLD OPERATIONS
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Pub. No.: WO/2017/152191 International Application No.: PCT/US2017/021015
Publication Date: 08.09.2017 International Filing Date: 06.03.2017
IPC:
H01L 27/088 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-shinjuku 6-chome Shinjuku-ku, Tokyo, 160-8366, JP (JP)
Inventors:
WU, Xiaoju; US
THOMPSON, C., Matthew; US
Agent:
DAVIS, Jr., Michael A.; US
Common
Representative:
TEXAS INSTRUMENTS INCORPORATED; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
Priority Data:
15/060,73604.03.2016US
Title (EN) MOSFET TRANSISTORS WITH ROBUST SUBTHRESHOLD OPERATIONS
(FR) TRANSISTORS À EFFET DE CHAMP MÉTAL-OXYDE SEMI-CONDUCTEURS (MOSFET) AYANT DES OPÉRATIONS DE SOUS-SEUIL ROBUSTES
Abstract:
(EN) In described examples of an integrated circuit with transistor regions (106) formed on a substrate, each transistor region (106) includes a channel region (116) and a terminal region (112, 114). The channel region (116) is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region (112, 114) is positioned adjacent to the channel region (116), and it is doped with a first dopant of a first conductivity type. Each transistor region (106) may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region (116) doped with a dopant and having a first doping concentration. Each transistor region (106) may include an edge recovery region (218) overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
(FR) Dans des exemples décrits d'un circuit intégré comprenant des régions de transistor (106) formées sur un substrat, chaque région de transistor (106) comprend une région de canal (116) et une région de terminal (112, 114). La région de canal (116) est positionnée le long d'une dimension transversale, et elle comprend une région de bord de canal le long d'une dimension longitudinale. La région de terminal (112, 114) est positionnée de manière adjacente à la région de canal (116), et elle est dopée avec un premier dopant d'un premier type de conductivité. Chaque région de transistor (106) peut comprendre une région de bloc de bord, qui est positionnée le long de la dimension longitudinale et adjacente à la région de bord de canal. La région de bloc de bord est dopée avec un second dopant d'un second type de conductivité opposé au premier type de conductivité. La région de canal (116) est dopée avec un dopant et a une première concentration de dopage. Chaque région de transistor (106) peut comprendre une région de récupération de bord (218) se chevauchant avec la région de bord de canal et ayant une seconde concentration de dopage supérieure à la première concentration de dopage.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)