Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2017151982) HIGH-RESOLUTION POWER ELECTRONICS MEASUREMENTS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/151982 International Application No.: PCT/US2017/020535
Publication Date: 08.09.2017 International Filing Date: 02.03.2017
IPC:
G01R 19/00 (2006.01) ,G01R 31/26 (2014.01) ,G01R 27/02 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
19
Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26
Testing of individual semiconductor devices
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
27
Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
02
Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku, Tokyo, 160-8366, JP (JP)
Inventors:
BAHL, Sandeep, R.; US
SMITH, Grant, L.; US
RUIZFLORES, Daniel; US
Agent:
DAVIS, Jr. Michael A.; US
Common
Representative:
TEXAS INSTRUMENTS INCORPORATED; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
Priority Data:
15/058,44402.03.2016US
Title (EN) HIGH-RESOLUTION POWER ELECTRONICS MEASUREMENTS
(FR) MESURES ÉLECTRONIQUES DE PUISSANCE À HAUTE RÉSOLUTION
Abstract:
(EN) In described examples of a measurement circuit to measure a drain voltage of a drain terminal (106) of the high voltage transistor (M0) during switching, the measurement circuit includes an attenuator circuit (102) to generate an attenuator output signal (VDCLAMP) representing a voltage across the high voltage transistor (M0) when the high voltage transistor (M0) is turned on, and a differential amplifier (124) to provide an amplified sense voltage signal (VO) according to the attenuator output signal (VDCLAMP). The attenuator circuit (102) includes a clamp transistor (M1) coupled with the drain terminal (106) of the high voltage transistor (M0) to provide a sense signal (VSENSE) to a first internal node (110), a resistive voltage divider circuit (116) to provide the attenuator output signal (VDCLAMP) based on the sense signal (VSENSE), and a first clamp circuit (Z1) to limit the sense signal voltage (VSENSE) when the high voltage transistor (M0) is turned off.
(FR) Dans des exemples de l’invention d’un circuit de mesure pour mesurer une tension de drain d’une borne de drain (106) du transistor à haute tension (M0) pendant une commutation, le circuit de mesure comprend un circuit atténuateur (102) pour générer un signal de sortie d’atténuateur (VDCLAMP) représentant une tension de part et d’autre du transistor à haute tension (M0) lorsque le transistor à haute tension (M0) est activé, et un amplificateur différentiel (124) pour produire un signal de tension de détection amplifié (V0) en fonction du signal de sortie d’atténuateur (VDCLAMP). Le circuit atténuateur (102) comprend un transistor de blocage (M1) couplé à la borne de drain (106) du transistor à haute tension (M0) pour transmettre un signal de détection (VSENSE) à un premier nœud interne (110), un circuit diviseur de tension résistive (116) pour fournir le signal de sortie d’atténuateur (VDCLAMP) sur la base du signal de détection (VSENSE), et un premier circuit de blocage (Z1) pour limiter la tension de signal de détection (VSENSE) lorsque le transistor à haute tension (M0) est désactivé.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)