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1. (WO2017151383) SELECTIVE SIARC REMOVAL
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Pub. No.: WO/2017/151383 International Application No.: PCT/US2017/019116
Publication Date: 08.09.2017 International Filing Date: 23.02.2017
IPC:
G03F 7/09 (2006.01) ,G03F 1/00 (2012.01) ,G03F 1/46 (2012.01) ,H01L 21/027 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/47 (2006.01)
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
7
Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
004
Photosensitive materials
09
characterised by structural details, e.g. supports, auxiliary layers
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1
Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
1
Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
38
Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
46
Antireflective coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
46
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428142
461
to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
469
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
47
Organic layers, e.g. photoresist
Applicants:
TOKYO ELECTRON LIMITED [JP/JP]; Akasaka Biz Tower 3-1 Akasaka 5-chome Minato-ku, Tokyo 107-6325, JP
TOKYO ELECTRON U.S. HOLDINGS, INC. [US/US]; 2400 Grove Boulevard Austin, Texas 78741, US (JP)
Inventors:
SRIDHAR, Shyam; US
WANG, Li; US
NOLAN, Andrew; US
OHTAKE, Hiroto; US
VORONIN, Sergey; US
RANJAN, Alok; JP
Agent:
DAVIDSON, Kristi L.; US
Priority Data:
62/301,38629.02.2016US
62/445,04211.01.2017US
Title (EN) SELECTIVE SIARC REMOVAL
(FR) ÉLIMINATION SÉLECTIVE DE REVÊTEMENT ANTIREFLET DE SILICIUM (SIARC)
Abstract:
(EN) Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.
(FR) L'invention concerne des procédés et des systèmes d'élimination sélective de revêtement antireflet de silicium (SiARC). Un mode de réalisation d'un procédé consiste à placer un substrat dans une chambre de traitement, le substrat comportant : une couche de réserve, une couche de SiARC, une couche de transfert de motif et une couche sous-jacente. Un tel procédé peut également consister à exécuter un processus de transfert de motif conçu pour éliminer la couche de réserve et créer une structure sur le substrat, la structure comprenant des parties de la couche de SiARC et de la couche de transfert de motif. Le procédé peut en outre consister à exécuter un processus de modification sur la couche de SiARC de la structure, la modification convertissant la couche de SiARC en une couche de SiARC poreuse. En outre, le procédé peut consister à exécuter un processus d'élimination de la couche de SiARC poreuse de la structure, les processus de modification et d'élimination de la couche de SiARC étant conçus pour satisfaire des objectifs d'intégration cibles.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)