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1. (WO2017151302) SYSTEM AND METHOD FOR REDUCING PROGRAMMING VOLTAGE STRESS ON MEMORY CELL DEVICES

Pub. No.:    WO/2017/151302    International Application No.:    PCT/US2017/017725
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Tue Feb 14 00:59:59 CET 2017
IPC: G11C 8/08
G11C 8/14
G11C 8/12
G11C 17/16
G11C 17/18
Applicants: QUALCOMM INCORPORATED
Inventors: YOON, Sei Seung
KOTA, Anil
GRUBELICH, Bjorn
Title: SYSTEM AND METHOD FOR REDUCING PROGRAMMING VOLTAGE STRESS ON MEMORY CELL DEVICES
Abstract:
A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to first and second sets of bit lines, respectively. The first subarray includes rows of memory cells coupled to a first set of local word line drivers via a first set of local word lines, respectively. The second subarray includes rows of memory cells coupled to a second set of local word line drivers via a second set of local word lines, respectively. A selected local word line drivers generates a first asserted local word line signal for accessing at least one memory cell for reading or programming purpose in response to receiving a second asserted signal via a global word line and a third asserted signal.