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1. (WO2017151296) MULTI-STEP VOLTAGE FOR FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELL FILAMENT

Pub. No.:    WO/2017/151296    International Application No.:    PCT/US2017/017543
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Sat Feb 11 00:59:59 CET 2017
IPC: H01L 45/00
G11C 11/00
G11C 11/02
G11C 13/00
Applicants: SILICON STORAGE TECHNOLOGY, INC.
AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventors: ZHOU, Feng
LIU, Xian
TRAN, Hieu, Van
NGUYEN, Hung, Quoc
DO, Nhan
REITEN, Mark
CHEN, Zhixian
XINPENG, Wang
LO, Guo-Qiang
Title: MULTI-STEP VOLTAGE FOR FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELL FILAMENT
Abstract:
A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.