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1. (WO2017151267) FLATTENING PORTAL BRIDGE

Pub. No.:    WO/2017/151267    International Application No.:    PCT/US2017/016302
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Fri Feb 03 00:59:59 CET 2017
IPC: G06F 12/02
G06F 13/40
Applicants: INTEL CORPORATION
Inventors: HARRIMAN, David J.
ROZIC, Reuven
DAN, Maxim
SETHI, Prashant
GOUGH, Robert E.
RABINDRANATH, Shanthanand Kutuva
Title: FLATTENING PORTAL BRIDGE
Abstract:
A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.