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1. (WO2017151253) SLIT STRESS MODULATION IN SEMICONDUCTOR SUBSTRATES

Pub. No.:    WO/2017/151253    International Application No.:    PCT/US2017/015377
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Sat Jan 28 00:59:59 CET 2017
IPC: H01L 21/762
H01L 21/8234
H01L 21/8238
H01L 27/118
Applicants: INTEL CORPORATION
Inventors: MATHEW, James
HO, Yunjun
XIE, Zhiqiang
KIM, Hyun Sik
Title: SLIT STRESS MODULATION IN SEMICONDUCTOR SUBSTRATES
Abstract:
A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.