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1. (WO2017150980) QUANTUM DOT CIRCUIT AND A METHOD OF CHARACTERIZING SUCH A CIRCUIT
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Pub. No.: WO/2017/150980 International Application No.: PCT/NL2017/050132
Publication Date: 08.09.2017 International Filing Date: 06.03.2017
IPC:
B82Y 10/00 (2011.01) ,H01L 29/423 (2006.01) ,H01L 29/76 (2006.01) ,H01L 29/12 (2006.01) ,G11C 11/34 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
82
NANO-TECHNOLOGY
Y
SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE  OR TREATMENT OF NANO-STRUCTURES
10
Nano-technology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
Applicants:
NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO [NL/NL]; Anna van Buerenplein 1 2595 DA 's-Gravenhage, NL
Inventors:
EENDEBAK, Pieter Thijs; NL
BAART, Timothy Alexander; NL
VANDERSYPEN, Lieven Mark Koenraad; NL
Agent:
JANSEN, C.M.; NL
Priority Data:
16158810.804.03.2016EP
Title (EN) QUANTUM DOT CIRCUIT AND A METHOD OF CHARACTERIZING SUCH A CIRCUIT
(FR) CIRCUIT À POINTS QUANTIQUES ET PROCÉDÉ DE CARACTÉRISATION D'UN TEL CIRCUIT
Abstract:
(EN) Quantum dot circuit and a method of characterizing such a circuit Voltages that enable control of electron occupation in a series of quantum dots are determined by a method of measuring effects of gate electrode voltages on a quantum dot circuit. The quantum dot circuit comprises a channel (10), first gate electrodes (14a-14e) that extend over locations along the edge of the channel to create potentials barriers defining the potentials well therebetween, as well as second gate electrodes (16a-16d) adjacent to potential wells, for controlling depths of the successive electrical potential wells between the potential barriers. First, channel currents are measured in a pre-scan of bias voltages of the first gates for controlling the potential barriers. The result is used to set their bias levels in, a scan over a two-dimensional range of combinations of bias voltages on the second gates for controlling the depths. In this scan an indication of charge carrier occupation of potential wells at consecutive positions along the channel such as electromagnetic wave reflection is measured. Pattern matching with a pattern of crossing occupation edges is applied to the result. This involves a two-dimensional image that has the combinations of the bias voltages as image points and the indication of charge carrier occupation as image values. The pattern matching detects an image point where the image matches a pattern of crossing edges along predetermined directions.
(FR) L'invention concerne un circuit à points quantiques et un procédé de caractérisation d'un tel circuit. Des tensions qui permettent la commande de l'occupation d'électrons dans une série de points quantiques sont déterminées par un procédé de mesure des effets de tensions d'électrode de grille sur un circuit à points quantiques. Le circuit à points quantiques comprend un canal (10), des premières électrodes de grille (14a-14e) qui s'étendent sur des emplacements le long du bord du canal pour créer des barrières de potentiel définissant des puits de potentiel entre elles, ainsi que des secondes électrodes de grille (16a-16d) adjacentes aux puits de potentiel, pour commander des profondeurs des puits de potentiel électrique successifs entre les barrières de potentiel. D'abord, des courants de canal sont mesurés dans un pré-balayage de tensions de polarisation des premières grilles pour commander les barrières de potentiel. Le résultat est utilisé pour régler leurs niveaux de polarisation dans un balayage sur une plage bidimensionnelle de combinaisons de tensions de polarisation sur les secondes grilles pour commander les profondeurs. Dans ce balayage, une indication d'occupation de porteurs de charge de puits de potentiel à des positions consécutives le long du canal, telle qu'une réflexion d'onde électromagnétique, est mesurée. Un appariement de motifs avec un motif de bords d'occupation croisés est appliqué au résultat. Ceci implique une image bidimensionnelle qui comprend les combinaisons des tensions de polarisation en tant que points d'image et l'indication d'occupation de porteurs de charge en tant que valeurs d'image. La mise en correspondance de motifs détecte un point d'image où l'image correspond à un motif de bords croisés le long de directions prédéterminées.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Licensing availability request The applicant has requested the International Bureau to indicate the availability for licensing purposes of the invention(s) claimed in this international application