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1. (WO2017150586) LAMINATE, ELECTRONIC DEVICE, AND PRODUCTION METHOD FOR LAMINATE
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Pub. No.: WO/2017/150586 International Application No.: PCT/JP2017/008026
Publication Date: 08.09.2017 International Filing Date: 28.02.2017
IPC:
B32B 7/02 (2006.01) ,B32B 9/00 (2006.01) ,B32B 27/20 (2006.01) ,C08K 9/04 (2006.01) ,C08L 63/02 (2006.01) ,H01L 23/36 (2006.01) ,H01L 23/373 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
7
Layered products characterised by the relation between layers, i.e. products essentially comprising layers having different physical properties or products characterised by the interconnection of layers
02
in respect of physical properties, e.g. hardness
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
9
Layered products essentially comprising a particular substance not covered by groups B32B11/-B32B29/137
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
27
Layered products essentially comprising synthetic resin
18
characterised by the use of special additives
20
using fillers, pigments, thixotroping agents
C CHEMISTRY; METALLURGY
08
ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
K
USE OF INORGANIC OR NON-MACROMOLECULAR ORGANIC SUBSTANCES AS COMPOUNDING INGREDIENTS
9
Use of pretreated ingredients
04
Ingredients treated with organic substances
C CHEMISTRY; METALLURGY
08
ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
L
COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
63
Compositions of epoxy resins; Compositions of derivatives of epoxy resins
02
Polyglycidyl ethers of bis-phenols
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373
Cooling facilitated by selection of materials for the device
Applicants:
JNC株式会社 JNC CORPORATION [JP/JP]; 東京都千代田区大手町二丁目2番1号 2-1, Otemachi 2-chome, Chiyoda-ku, Tokyo 1008105, JP
地方独立行政法人大阪産業技術研究所 OSAKA RESEARCH INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY [JP/JP]; 大阪府和泉市あゆみ野2丁目7番1号 7-1, Ayumino 2-chome, Izumi-shi, Osaka 5941157, JP
Inventors:
藤原 武 FUJIWARA,Takeshi; JP
稲垣 順一 INAGAKI, Jyunichi; JP
上利 泰幸 AGARI, Yasuyuki; JP
平野 寛 HIRANO, Hiroshi; JP
門多 丈治 KADOTA, Joji; JP
岡田 哲周 OKADA, Akinori; JP
Agent:
宮川 貞二  MIYAGAWA, Teiji; JP
金子 美代子 KANEKO, Miyoko; JP
Priority Data:
2016-04052202.03.2016JP
Title (EN) LAMINATE, ELECTRONIC DEVICE, AND PRODUCTION METHOD FOR LAMINATE
(FR) STRATIFIÉ, DISPOSITIF ÉLECTRONIQUE, ET PROCÉDÉ DE PRODUCTION POUR STRATIFIÉ
(JA) 積層体、電子機器、積層体の製造方法
Abstract:
(EN) The present invention is a laminate: with which differences in the thermal expansion coefficient at interfaces between different materials in the interior of a semiconductor element or the like can be kept small; which has high heat resistance; and which has high thermal conductivity. This laminate is provided with at least two layers of thermal expansion-controlling members, the thermal expansion-controlling members including a thermally conductive first inorganic filler joined to one end of a first coupling agent, and a thermally conductive second inorganic filler joined to one end of a second coupling agent; the other end of the first coupling agent and the other end of the second coupling agent are respectively joined to a polymerizable compound, or joined to one another; and the thermal expansion-controlling members have thermal expansion coefficients that are respectively different.
(FR) La présente invention concerne un stratifié, avec lequel stratifié des différences dans le coefficient de dilatation thermique à des interfaces entre des matériaux différents à l'intérieur d'un élément semi-conducteur, ou analogue, peuvent être maintenues faibles; lequel a une résistance thermique élevée; et lequel a une conductivité thermique élevée. Ce stratifié comporte au moins deux couches d'éléments de régulation de dilatation thermique, les éléments de régulation de dilatation thermique comprenant une première charge minérale thermiquement conductrice réunie à une extrémité d'un premier agent de couplage, et une seconde charge minérale thermiquement conductrice réunie à une extrémité d'un second agent de couplage; l'autre extrémité du premier agent de couplage et l'autre extrémité du second agent de couplage étant respectivement réunies à un composé polymérisable, ou réunies l'une à l'autre; et les éléments de régulation de dilatation thermique ayant des coefficients de dilatation thermique qui sont respectivement différents.
(JA) 本発明は、半導体素子内部等において、異なる材料間の界面の熱膨張率の差を小さくでき、高耐熱性を有し、さらに熱伝導率も高い積層体である。本発明の積層体は、熱膨張制御部材を少なくとも2層備える積層体であって:前記熱膨張制御部材は、第1のカップリング剤の一端と結合した熱伝導性の第1の無機フィラーと;第2のカップリング剤の一端と結合した熱伝導性の第2の無機フィラーと;を含み、前記第1のカップリング剤の他端と前記第2のカップリング剤の他端が、それぞれ重合性化合物に結合した熱膨張制御部材、または、互いに結合した熱膨張制御部材であり、前記熱膨張制御部材の熱膨張率がそれぞれ異なる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)