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1. (WO2017150452) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2017/150452 International Application No.: PCT/JP2017/007510
Publication Date: 08.09.2017 International Filing Date: 27.02.2017
IPC:
H01L 29/78 (2006.01) ,H01L 21/316 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314
Inorganic layers
316
composed of oxides or glassy oxides or oxide-based glass
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
富士電機株式会社 FUJI ELECTRIC CO., LTD. [JP/JP]; 神奈川県川崎市川崎区田辺新田1番1号 1-1, Tanabeshinden, Kawasaki-ku, Kawasaki-shi, Kanagawa 2109530, JP
Inventors:
上野 勝典 UENO Katsunori; JP
中川 清和 NAKAGAWA Kiyokazu; JP
Agent:
龍華国際特許業務法人 RYUKA IP LAW FIRM; 東京都新宿区西新宿1-6-1 新宿エルタワー22階 22F, Shinjuku L Tower, 1-6-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2016-03758829.02.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ POUR FABRIQUER UN DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置および半導体装置の製造方法
Abstract:
(EN) A SiO2 film may become contaminated by carbon (C) when the SiO2 film is to be formed on a semiconductor substrate using TEOS (tetraethylorthosilicate: Si (OC2H5)4). Carbon can function as a fixed charge in the SiO2 film. For example, when carbon (C) contaminates the SiO2 film serving as as a gate insulating film of a metal–oxide–semiconductor field-effect transistor (MOSFET), there is the problem in that the gate threshold voltage (Vth) fluctuates. Provided is a semiconductor device which uses a gallium nitride semiconductor layer, wherein the semiconductor device has at least a portion provided in direct contact with the gallium nitride layer, and is provided with a silicon dioxide film having impurity atoms, the silicon dioxide film containing, as the impurity atoms, carbon at a concentration greater than 0 cm–3 and less than 2E+18 cm–3, and gallium at a concentration of 1E+17 cm–3 or less.
(FR) Le problème à résoudre dans le cadre de la présente invention est qu'un film de SiO2 peut être contaminé par du carbone (C) lorsque le film de SiO2 doit être formé sur un substrat à semi-conducteur en utilisant du TEOS (tétraéthylorthosilicate : Si (OC2H5)4). Le carbone peut servir de charge fixe dans le film de SiO2. Par exemple, lorsque du carbone (C) contamine le film de SiO2 qui sert de film d'isolation de grille d'un transistor à effet de champ métal-oxyde-semi-conducteur (MOSFET), il existe un problème car la tension de seuil de grille (Vth) fluctue. La solution proposée consiste en un dispositif à semi-conducteur qui utilise une couche de semi-conducteur de nitrure de gallium, le dispositif à semi-conducteur possédant au moins une partie prévue en contact direct avec la couche de nitrure de gallium, et étant pourvu d'un film de dioxyde de silicium qui contient, en tant qu'atomes d'impureté, du carbone à une concentration supérieure à 0 cm–3 et inférieure à 2E+18 cm–3, et du gallium à une concentration de 1E+17 cm–3 ou moins.
(JA) TEOS(オルトケイ酸テトラエチル:Si(OC)を用いて半導体基板上にSiO膜を形成する場合、当該SiO膜に炭素(C)が混入する場合がある。SiO膜に炭素は固定電荷として機能し得る。例えば、MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)のゲート絶縁膜としてのSiO膜に炭素(C)が混入した場合、ゲート閾値電圧(Vth)が変動する問題がある。窒化ガリウム半導体層を用いた半導体装置であって、少なくとも一部が窒化ガリウム半導体層に直接接して設けられ、不純物原子を有する二酸化シリコン膜を備え、二酸化シリコン膜は、不純物原子として、0cm-3より大きく2E+18cm-3未満の濃度の炭素と、1E+17cm-3以下の濃度のガリウムを含む半導体装置を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)