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1. (WO2017150157) METHOD FOR POLISHING SILICON SUBSTRATE AND POLISHING COMPOSITION SET
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Pub. No.: WO/2017/150157 International Application No.: PCT/JP2017/005139
Publication Date: 08.09.2017 International Filing Date: 13.02.2017
IPC:
H01L 21/304 (2006.01) ,B24B 37/00 (2012.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
B PERFORMING OPERATIONS; TRANSPORTING
24
GRINDING; POLISHING
B
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
37
Lapping machines or devices; Accessories
Applicants:
株式会社フジミインコーポレーテッド FUJIMI INCORPORATED [JP/JP]; 愛知県清須市西枇杷島町地領二丁目1番地1 1-1, Chiryo 2-chome, Nishibiwajima-cho, Kiyosu-shi, Aichi 4528502, JP
Inventors:
田畑 誠 TABATA, Makoto; JP
Agent:
安部 誠 ABE Makoto; JP
Priority Data:
2016-03724729.02.2016JP
Title (EN) METHOD FOR POLISHING SILICON SUBSTRATE AND POLISHING COMPOSITION SET
(FR) PROCÉDÉ PERMETTANT DE POLIR UN SUBSTRAT DE SILICIUM ET ENSEMBLE DE COMPOSITION DE POLISSAGE
(JA) シリコン基板の研磨方法および研磨用組成物セット
Abstract:
(EN) Provided are: a silicon substrate polishing method which is capable of reducing PID; and a polishing composition set which is used in this polishing method. A silicon substrate polishing method according to the present invention comprises a preliminary polishing process and a finish polishing process. The preliminary polishing process comprises a plurality of preliminary polishing steps that are performed on a same polishing plate. The plurality of preliminary polishing steps include a final preliminary polishing step that is performed while supplying a final preliminary polishing slurry PF to a silicon substrate. At least one of the total Cu weight and the total Ni weight in the final preliminary polishing slurry PF supplied to the silicon substrate in the final preliminary polishing step is 1 μg or less.
(FR) La présente invention concerne : un procédé de polissage de substrat de silicium qui peut réduire le PID ; et un ensemble de composition de polissage qui est utilisé dans ce procédé de polissage. Un procédé de polissage de substrat de silicium selon la présente invention comprend un processus de polissage préliminaire et un processus de polissage de finition. Le processus de polissage préliminaire comprend une pluralité d'étapes de polissage préliminaire qui sont exécutées sur une même plaque de polissage. La pluralité d'étapes de polissage préliminaire comprennent une dernière étape de polissage préliminaire qui est effectuée tout en fournissant une dernière suspension de polissage préliminaire (PF) sur un substrat de silicium. Le poids total de cuivre (Cu) et/ou le poids total de nickel (Ni) dans la dernière suspension de polissage préliminaire (PF) fournie au substrat de silicium au cours de la dernière étape de polissage préliminaire sont égaux ou inférieurs à 1 µg.
(JA) PIDを低減し得るシリコン基板研磨方法および該研磨方法に用いられる研磨用組成物セットが提供される。本発明により提供されるシリコン基板研磨方法は、予備研磨工程と仕上げ研磨工程とを含む。上記予備研磨工程は、同一定盤上で行われる複数の予備研磨段階を含む。上記複数の予備研磨段階は、上記シリコン基板に最終予備研磨スラリーPを供給して行われる最終予備研磨段階を含む。上記最終予備研磨段階において上記シリコン基板に供給される全最終予備研磨スラリーP中の総Cu重量および総Ni重量の少なくとも一方は1μg以下である。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)