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1. (WO2017150146) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
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Pub. No.: WO/2017/150146 International Application No.: PCT/JP2017/004961
Publication Date: 08.09.2017 International Filing Date: 10.02.2017
IPC:
H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/522 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants:
パナソニック・タワージャズセミコンダクター株式会社 TOWERJAZZ PANASONIC SEMICONDUCTOR CO., LTD. [JP/JP]; 富山県魚津市東山800番地 800 Higashiyama, Uozu City, Toyama 9378585, JP
Inventors:
井上 由佳 INOUE Yuka; JP
福羅 満徳 FUKURA Mitsunori; JP
高橋 信義 TAKAHASHI Nobuyoshi; JP
小田 真弘 ODA Masahiro; JP
矢野 尚 YANO Hisashi; JP
伊藤 豊 ITO Yutaka; JP
森永 泰規 MORINAGA Yasunori; JP
Agent:
特許業務法人前田特許事務所 MAEDA & PARTNERS; 大阪府大阪市北区堂島浜1丁目2番1号 新ダイビル23階 Shin-Daibiru Bldg. 23F, 2-1, Dojimahama 1-chome, Kita-ku, Osaka-shi, Osaka 5300004, JP
Priority Data:
2016-03662229.02.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) This semiconductor device is provided with: a first interlayer film 2 that is formed on the upper surface of a substrate 1; a first metal wiring line 3; a second interlayer film 5; a second metal wiring line 11; a first via 10 that electrically connects the first metal wiring line 3 and the second metal wiring line 11 to each other; a landing pad 12 that penetrates through the second interlayer film 5 and is buried in the upper part of the first interlayer film 2; and a second via 25 that penetrates through the substrate 1 and the first interlayer film 2 from the back surface side of the substrate 1 and is connected to the landing pad 12. In this connection, the position of the lower surface of the landing pad 12 is different from the position of the lower surface of the first metal wiring line 3.
(FR) La présente invention concerne un dispositif à semi-conducteur qui comprend : un premier film inter couche (2) qui est formé sur la surface supérieure d'un substrat (1) ; une première ligne de câblage métallique (3) ; un second film intercouche (5) ; une seconde ligne de câblage métallique (11) ; un premier trou d'interconnexion (10) qui raccorde électriquement la première ligne de câblage métallique (3) et la seconde ligne de câblage métallique (11) l'une à l'autre ; une plage de connexion (12) qui pénètre dans le second film intercouche (5) et est enfouie dans la partie supérieure du premier film intercouche (2) ; et un second trou d'interconnexion (25) qui pénètre par le substrat (1) et le premier film intercouche (2) depuis le côté de surface arrière du substrat (1) et est raccordé à la plage de connexion (12). A cet égard, la position de la surface inférieure de la plage de connexion (12) est différente de la position de la surface inférieure de la première ligne de câblage métallique (3).
(JA) 半導体装置は、基板1の上面上に形成された第1の層間膜2と、第1の金属配線3と、第2の層間膜5と、第2の金属配線11と、第1の金属配線3と第2の金属配線11とを電気的に接続する第1のビア10と、第1の層間膜2の上部に埋め込まれるとともに、第2の層間膜5を貫通するランディングパッド12と、基板1の裏面側から基板1及び第1の層間膜2を貫通し、ランディングパッド12に接続する第2のビア25とを備え、ランディングパッド12の下面位置は、第1の金属配線3の下面位置と異なっている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)