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1. (WO2017150080) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
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Pub. No.: WO/2017/150080 International Application No.: PCT/JP2017/004207
Publication Date: 08.09.2017 International Filing Date: 06.02.2017
IPC:
H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01)
[IPC code unknown for H01L 21/3205][IPC code unknown for H01L 21/768][IPC code unknown for H01L 23/522]
Applicants:
株式会社アドバンテスト ADVANTEST CORPORATION [JP/JP]; 東京都練馬区旭町1丁目32番1号 1-32-1, Asahi-cho, Nerima-ku, Tokyo 1790071, JP
Inventors:
岡安 潤一 OKAYASU, Jun'ichi; JP
阿部 善亮 ABE, Yoshiaki; JP
大泉 卓也 OIZUMI, Takuya; JP
八城 貴浩 YASHIRO, Takahiro; JP
Agent:
森下 賢樹 MORISHITA Sakaki; JP
Priority Data:
2016-03677429.02.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体デバイスおよびその製造方法
Abstract:
(EN) In a semiconductor device 100, an episubstrate 102 includes a SiC (silicon carbide) substrate and an epilayer of GaN (gallium nitride) formed on the SiC substrate. A multilayer wiring structure 300 is formed on the front surface side of the episubstrate 102 and includes at least one metal wire layer M1 and an organic interlayer insulating film. A rear surface metal layer 120 is formed on the rear surface of the episubstrate 102. At least one via hole 122 is formed in the episubstrate 102 and connects between the multilayer wiring structure 300 and the rear surface metal layer 120.
(FR) Dans un dispositif à semi-conducteur 100 selon l'invention, un épisubstrat 102 comprend un substrat de SiC (carbure de silicium) et une épicouche de GaN (nitrure de gallium) formée sur le substrat de SiC. Une structure de câblage multicouche 300 est formée sur le côté de surface avant de l'épisubstrat 102 et comprend au moins une couche de fil métallique M1 et un film isolant intercouche organique. Une couche métallique de surface arrière 120 est formée sur la surface arrière de l'épisubstrat 102. Au moins un trou d'interconnexion 122 est formé dans l'épisubstrat 102 et relie la structure de câblage multicouche 300 et la couche métallique de surface arrière 120.
(JA) 半導体デバイス100において、エピ基板102は、SiC(炭化珪素)基板およびSiC基板上に形成されるGaN(窒化ガリウム)のエピ層を含む。多層配線構造300は、エピ基板102の表面側に形成されており、少なくともひとつの金属配線層M1および有機系の層間絶縁膜を含む。裏面メタル層120は、エピ基板102の裏面に形成される。少なくともひとつのビアホール122は、エピ基板102に形成され、多層配線構造300と裏面メタル層120の間を接続する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)