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1. (WO2017149956) SIGNAL OUTPUT CIRCUIT
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Pub. No.: WO/2017/149956 International Application No.: PCT/JP2017/001215
Publication Date: 08.09.2017 International Filing Date: 16.01.2017
IPC:
H03K 17/16 (2006.01) ,H03K 4/56 (2006.01) ,H03K 5/12 (2006.01) ,H03K 19/0175 (2006.01) ,H04L 25/03 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
16
Modifications for eliminating interference voltages or currents
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
4
Generating pulses having essentially a finite slope or stepped portions
06
having triangular shape
08
having sawtooth shape
48
using as active elements semiconductor devices
50
in which a sawtooth voltage is produced across a capacitor
56
using a semiconductor device with negative feedback through a capacitor, e.g. Miller integrator
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
5
Manipulating pulses not covered by one of the other main groups in this subclass
01
Shaping pulses
12
by steepening leading or trailing edges
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
25
Baseband systems
02
Details
03
Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
Applicants:
株式会社デンソー DENSO CORPORATION [JP/JP]; 愛知県刈谷市昭和町1丁目1番地 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
Inventors:
岡 典正 OKA, Norimasa; JP
川合 博史 KAWAGO, Hiroshi; JP
Agent:
特許業務法人 サトー国際特許事務所 SATO INTERNATIONAL PATENT FIRM; JP
Priority Data:
2016-03895301.03.2016JP
Title (EN) SIGNAL OUTPUT CIRCUIT
(FR) CIRCUIT DE SORTIE DE SIGNAL
(JA) 信号出力回路
Abstract:
(EN) This signal output circuit (1, 51) comprises a slope control circuit (6), a capacitor (9), a noise detection circuit (14, 31, 41) and a malfunction prevention circuit (7). The slope control circuit charges and discharges the capacitor, the first terminal of which is connected to an output terminal (4), according to the control signal IN level, and drives transistors (3, 52) using the voltage Vc of the second terminal of the capacitor, thereby controlling the slope of the output signal OUT. The noise detection circuit detects noise superimposed on the output terminal. When noise is detected, the malfunction prevention circuit performs a forced drive operation of the transistor in such a manner that an output signal OUT with a level corresponding to the level of the control signal IN is output, regardless of the driving of the transistor by the slope control circuit.
(FR) La présente invention concerne un circuit de sortie de signal (1, 51) comportant un circuit de commande de pente (6), un condensateur (9), un circuit de détection de bruit (14, 31, 41) et un circuit de prévention de dysfonctionnement (7). Le circuit de commande de pente charge et décharge le condensateur, dont la première borne est connectée à une borne de sortie (4), en fonction du niveau du signal de commande IN, et commande des transistors (3, 52) au moyen de la tension Vc de la seconde borne du condensateur, permettant ainsi de contrôler la pente du signal de sortie OUT. Le circuit de détection de bruit détecte un bruit superposé à la borne de sortie. Lorsqu'un bruit est détecté, le circuit de prévention de dysfonctionnement effectue une opération de commande forcée du transistor de sorte qu'un signal de sortie OUT avec un niveau correspondant au niveau du signal de commande IN soit émis en sortie, indépendamment de la commande du transistor par le circuit de commande de pente.
(JA) 信号出力回路(1、51)は、スロープ制御回路(6)、キャパシタ(9)、ノイズ検出回路(14、31、41)および誤動作防止回路(7)を備える。前記スロープ制御回路は、制御信号INのレベルに応じて第1端子が出力端子(4)に接続された前記キャパシタの充電および放電を行い、前記キャパシタの第2端子の電圧Vcを用いてトランジスタ(3、52)を駆動することで出力信号OUTのスロープを制御する。前記ノイズ検出回路は、前記出力端子に重畳されるノイズを検出する。前記誤動作防止回路は、ノイズが検出されると、前記スロープ制御回路による前記トランジスタの駆動に関係なく、制御信号INのレベルに応じたレベルの出力信号OUTが出力されるように前記トランジスタを駆動する強制駆動動作を行う。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)