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1. (WO2017149926) SEMICONDUCTOR PROCESSING SHEET
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Pub. No.: WO/2017/149926 International Application No.: PCT/JP2017/000187
Publication Date: 08.09.2017 International Filing Date: 05.01.2017
IPC:
H01L 21/301 (2006.01) ,B32B 27/00 (2006.01) ,C09J 7/02 (2006.01) ,H01L 21/304 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
27
Layered products essentially comprising synthetic resin
C CHEMISTRY; METALLURGY
09
DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
J
ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
7
Adhesives in the form of films or foils
02
on carriers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
Applicants:
リンテック株式会社 LINTEC CORPORATION [JP/JP]; 東京都板橋区本町23番23号 23-23, Honcho, Itabashi-ku, Tokyo 1730001, JP
Inventors:
佐藤 明徳 SATO Akinori; JP
中村 優智 NAKAMURA Masatomo; JP
山下 茂之 YAMASHITA Shigeyuki; JP
Agent:
早川 裕司 HAYAKAWA Yuzi; JP
村雨 圭介 MURASAME Keisuke; JP
飯田 理啓 IIDA Michihiro; JP
Priority Data:
2016-04286304.03.2016JP
Title (EN) SEMICONDUCTOR PROCESSING SHEET
(FR) FEUILLE DE TRAITEMENT DE SEMI-CONDUCTEUR
(JA) 半導体加工用シート
Abstract:
(EN) This semiconductor processing sheet 1 comprises at least: a substrate 10 including a first surface 101 and a second surface 102; a semiconductor bonding layer 80 including a first surface 801 and a second surface 802; and a peeling film 30 including a first surface 301 and a second surface 302. In the semiconductor processing sheet 1: the arithmetic mean roughness Ra of the first surface 101 is from 0.01 to 0.8 µm; the arithmetic mean roughness Ra of the second surface 302 is greater than 0.05 µm to 0.8 µm or less; and the peeling force β at the interface between the second surface 802 and the first surface 301 after bonding the second surface 802 and the first surface 301 and storing the same at 40°C for three days is from 10 to 1000 mN/50 mm. This semiconductor processing sheet 1 has excellent light transmissibility, and blocking is less likely to occur.
(FR) La présente invention concerne une feuille de traitement de semi-conducteur 1 qui comprend au moins : un substrat 10 comprenant une première surface 101 et une deuxième surface 102 de fixation de semi-conducteur 80 comprenant une première surface 801 et une deuxième surface 802 ; et un film pelable 30 comprenant une première surface 301 et une deuxième surface 302. Dans la feuille de traitement de semi-conducteur 1 : la rugosité moyenne arithmétique Ra de la première surface 101 est de 0,01 à 0,8 µm ; la rugosité moyenne arithmétique Ra de la deuxième surface 302 est de plus de 0,05 µm à 0,8 µm ou moins ; et la force de pelage β à l'interface entre la deuxième surface 802 et la première surface 301 après la fixation de la deuxième surface 802 et la première surface 301 et conservation de celles-ci à 40 °C pendant trois jours est de 10 à 1000 mN/50 mm. Cette feuille de traitement de semi-conducteur 1 présente une excellente transmission de lumière, et un blocage est moins susceptible de survenir.
(JA) 第1の面101および第2の面102を有する基材10と、第1の面801および第2の面802を有する半導体貼付層80と、第1の面301および第2の面302を有する剥離フィルム30とを少なくとも備える半導体加工用シート1であって、第1の面101における算術平均粗さRaが、0.01~0.8μmであり、第2の面302の算術平均粗さRaが、0.05μm超、0.8μm以下であり、第2の面802と第1の面301とを貼付して40℃で3日間保管した後における、第2の面802と第1の面301との界面での剥離力βが、10~1000mN/50mmである半導体加工用シート1。かかる半導体加工用シート1は、光線透過性に優れるとともに、ブロッキングが生じ難い。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)