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1. (WO2017149743) WIDE GAP SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/149743 International Application No.: PCT/JP2016/056732
Publication Date: 08.09.2017 International Filing Date: 04.03.2016
Chapter 2 Demand Filed: 05.09.2016
IPC:
H01L 29/06 (2006.01) ,H01L 29/872 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
Applicants:
新電元工業株式会社 SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. [JP/JP]; 東京都千代田区大手町二丁目2番1号 2-1, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP
Inventors:
前山 雄介 MAEYAMA, Yusuke; JP
中村 俊一 NAKAMURA, Shunichi; JP
Agent:
大野 聖二 OHNO, Seiji; JP
Priority Data:
Title (EN) WIDE GAP SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS À LARGE ESPACE
(JA) ワイドギャップ型半導体装置
Abstract:
(EN) A wide gap semiconductor device has: a first electrically conductive semiconductor layer 32; inner peripheral second electrically conductive regions 41, 42 provided on the first electrically conductive semiconductor layer 32; a first electrode 10; insulation layers 51, 52, 53 which are provided on the first electrically conductive semiconductor layer 32, adjacent to the first electrode 10, and extending to the end part of the wide gap semiconductor device; and an outer peripheral second electrically conductive region 20 provided on the outer periphery of the inner peripheral second electrically conductive regions 41, 42. The distance between the end part of the inner peripheral second electrically conductive regions 41, 42 and the end part of the outer peripheral second electrically conductive region 20 is greater than the width of the depletion layer that expands to the outer periphery from the inner peripheral second electrically conductive regions 41, 42.
(FR) L’invention concerne un dispositif à semi-conducteurs à large espace qui a : une première couche à semi-conducteurs électroconductrice (32) ; des secondes régions électroconductrices périphériques internes (41, 42) disposées sur la première couche à semi-conducteurs électroconductrice (32) ; une première électrode (10) ; des couches d’isolation (51, 52, 53) qui sont disposées sur la première couche à semi-conducteurs électroconductrice (32), adjacente à la première électrode (10), et s’étendant vers la partie d’extrémité du dispositif à semi-conducteurs à large espace ; et une seconde région électroconductrice périphérique externe (20) disposée sur la périphérie externe des secondes régions électroconductrices périphériques internes (41, 42). La distance entre la partie d’extrémité des secondes régions électroconductrices périphériques internes (41, 42) et la partie d’extrémité de la seconde région électroconductrice périphérique externe (20) est supérieure à la largeur de la couche d’appauvrissement qui s’étend vers la périphérie externe à partir des secondes régions électroconductrices périphériques internes (41, 42).
(JA) ワイドギャップ型半導体装置は、第1導電型半導体層32と、前記第1導電型半導体層32上に設けられた内周側第2導電型領域41,42と、第1電極10と、前記第1導電型半導体層32上であって前記第1電極10に隣接して設けられ、前記ワイドギャップ型半導体装置の端部まで延びた絶縁層51,52,53と、前記内周側第2導電型領域41,42の外周側に設けられた外周側第2導電型領域20と、を有している。前記内周側第2導電型領域41,42の端部と前記外周側第2導電型領域20の端部との間の距離は、前記内周側第2導電型領域41,42から外周側に広がる空乏層幅より大きくなっている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)