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1. (WO2017149641) SIMULATOR

Pub. No.:    WO/2017/149641    International Application No.:    PCT/JP2016/056198
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Wed Mar 02 00:59:59 CET 2016
IPC: G06F 11/28
Applicants: MITSUBISHI ELECTRIC CORPORATION
三菱電機株式会社
Inventors: OGAWA, Daisuke
小川 大佑
TOYAMA, Osamu
遠山 治
TAKEO, Tetsuya
武尾 哲也
NISHIKAWA, Koji
西川 浩司
Title: SIMULATOR
Abstract:
A multicore model simulator according to the present invention is characterized by being provided with: a plurality of processor core models for executing an inputted instruction; a processed time calculation unit for calculating a time of day, as a processed time, at which each of the processor core models has executed an instruction; a scheduler for selecting a next processor core model to execute from among the plurality of processor core models on the basis of the processed time calculated by the processed time calculation unit; and an overall time-holding unit for holding the overall processed time of the simulator that is determined from the processed time calculated by the processed time calculation unit, the processor core model selected by the scheduler executing a next instruction following directions of the scheduler. This configuration enables the accuracy of synchronization between multi-CPUs or multi-cores to be maintained while allowing the multi-CPUs or multi-cores to execute with different accuracies of execution, and makes accurate evaluation of performance possible.