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1. (WO2017149295) MULTIPLE DATA RATE MEMORY

Pub. No.:    WO/2017/149295    International Application No.:    PCT/GB2017/050540
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Wed Mar 01 00:59:59 CET 2017
IPC: G11C 11/419
G11C 7/06
G11C 7/08
G11C 7/12
G11C 7/10
G11C 8/16
G11C 7/22
G11C 7/18
Applicants: SURECORE LIMITED
Inventors: COSEMANS, Stefan
ROOSELEER, Bram
Title: MULTIPLE DATA RATE MEMORY
Abstract:
There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to- global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.