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1. (WO2017147968) COMPLEMENTARY THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/147968 International Application No.: PCT/CN2016/078749
Publication Date: 08.09.2017 International Filing Date: 08.04.2016
IPC:
H01L 27/092 (2006.01) ,H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号丁珂 Ding Ke No.9-2 Tangming Rd, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
曾勉 ZENG, Mian; CN
萧祥志 HSIAO, Hsiang Chih; CN
张盛东 ZHANG, Shengdong; CN
Agent:
深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT&TRADEMARK AGENCY; 中国广东省深圳市 福田区深南大道6021号喜年中心A座1709-1711 Hailrun Complex Block A Room 1709-1711 No.6021 Shennan Blvd, Futian District Shenzhen, Guangdong 518040, CN
Priority Data:
201610112863.729.02.2016CN
Title (EN) COMPLEMENTARY THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
(FR) TRANSISTOR À COUCHES MINCES COMPLÉMENTAIRE ET SON PROCÉDÉ DE FABRICATION
(ZH) 互补型薄膜晶体管及其制造方法
Abstract:
(EN) A complementary thin film transistor and a manufacturing method therefor. The complementary thin film transistor (100) comprises a substrate (2), an N-type semiconductor layer (31), and a P-type semiconductor layer (32). An N-type transistor region (101) and a P-type transistor region (102) that are adjacently disposed are defined by the substrate. The N-type semiconductor layer is disposed above the substrate and is located in the N-type transistor region, and the N-type semiconductor layer comprises a metal oxide material. The P-type semiconductor layer is disposed above the substrate and is located in the P-type transistor region, and the P-type semiconductor layer comprises an organic semiconductor material.
(FR) L'invention concerne un transistor à couches minces complémentaire et son procédé de fabrication. Le transistor à couches minces complémentaire (100) comprend un substrat, une couche semi-conductrice du type N (31) et une couche semi-conductrice du type P (32). Une zone de transistor du type N (101) et une zone de transistor du type P (102), qui sont disposées adjacentes l'une à l'autre, sont délimitées par le substrat. La couche semi-conductrice du type N est disposée au-dessus du substrat et se trouve dans la zone de transistor du type N, la couche semi-conductrice du type N comportant un matériau oxyde métallique. La couche semi-conductrice du type P est disposée au-dessus du substrat et se trouve dans la zone de transistor du type P, la couche semi-conductrice du type P comportant un matériau semi-conducteur organique.
(ZH) 一种互补型薄膜晶体管及其制造方法,该互补型薄膜晶体管(100)包含一基板(2)、一N型半导体层(31)及一P型半导体层(32);该基板定义有相邻的一N型晶体管区(101)及一P型晶体管区(102),该N型半导体层设置在该基板上方且位于该N型晶体管区中,且该N型半导体层包含一金属氧化物材料,该P型半导体层设置在该基板上方且位于该P型晶体管区中,且该P型半导体层包含一有机半导体材料。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)