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1. (WO2017147955) HARMONICS SUPPRESSION CIRCUIT FOR A SWITCH-MODE POWER AMPLIFIER

Pub. No.:    WO/2017/147955    International Application No.:    PCT/CN2016/077388
Publication Date: Sat Sep 09 01:59:59 CEST 2017 International Filing Date: Sat Mar 26 00:59:59 CET 2016
IPC: H03F 3/217
Applicants: HONG KONG APPLIED SCIENCE & TECHNOLOGY RESEARCH INSTITUTE COMPANY LIMITED
Inventors: ZHENG, Shiyuan
WU, Zhiwei
Title: HARMONICS SUPPRESSION CIRCUIT FOR A SWITCH-MODE POWER AMPLIFIER
Abstract:
Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.