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1. (WO2017147895) LOW-AREA LOW CLOCK-POWER FLIP-FLOP
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/147895 International Application No.: PCT/CN2016/075596
Publication Date: 08.09.2017 International Filing Date: 04.03.2016
IPC:
H03K 3/356 (2006.01) ,H03K 3/012 (2006.01) ,H03K 3/3562 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
01
Details
012
Modifications of generator to improve response time or to decrease power consumption
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
3562
of the master-slave type
Applicants:
RASOULI, Seid Hadi [IR/US]; US (US)
KANG, Hananel [US/US]; US (US)
CAI, Yanfei [CN/US]; US (US)
CHEN, Xiangdong [US/US]; US (US)
BOYNAPALLI, Venugopal [IN/US]; US (US)
QUALCOMM INCORPORATED [US/US]; 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
RASOULI, Seid Hadi; US
KANG, Hananel; US
CAI, Yanfei; US
CHEN, Xiangdong; US
BOYNAPALLI, Venugopal; US
Agent:
SHANGHAI PATENT & TRADEMARK LAW OFFICE, LLC; 435 Guiping Road Shanghai 200233, CN
Priority Data:
Title (EN) LOW-AREA LOW CLOCK-POWER FLIP-FLOP
(FR) BASCULE À ENCOMBREMENT RÉDUIT ET BASSE PUISSANCE D'HORLOGE
Abstract:
(EN) In one example, an apparatus may be a flip-flop that includes a slave latch and a master latch. The master latch includes a first logic element in the master latch. The first logic element includes a first transistor. The first transistor is shared by a second logic element in one of the master latch or the slave latch. The first transistor provides a clocking signal input to the first logic element and the second logic element.
(FR) Selon un exemple, un appareil selon l'invention peut être un bascule qui comprend un circuit à verrouillage esclave et un circuit à verrouillage maître. Le circuit à verrouillage maître comprend un premier élément logique dans le circuit à verrouillage maître. Le premier élément logique comprend un premier transistor. Le premier transistor est partagé par un second élément logique dans le circuit à verrouillage maître ou le circuit à verrouillage esclave. Le premier transistor fournit une entrée de signal d'horloge au premier élément logique et au second élément logique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)