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1. (WO2017139807) MEASURING INTERNAL SIGNALS OF AN INTEGRATED CIRCUIT
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/139807 International Application No.: PCT/US2017/017743
Publication Date: 17.08.2017 International Filing Date: 13.02.2017
IPC:
G01R 31/28 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
Applicants:
TEXAS INSTRUMENTS INCORPORATED [US/US]; P.O. Box 655474, Mail Station 3999 Dallas, TX 75265-5474, US
TEXAS INSTRUMENTS JAPAN LIMITED [JP/JP]; 24-1, Nishi-Shinjuku 6-chome Shinjuku-ku, Tokyo 160-8366, JP (JP)
Inventors:
MURTHY, Kushal, D.; IN
PARMAR, Manish; IN
TADEPARTHY, Preetam; IN
VENKATESWARAN, Muthusubramanian; IN
Agent:
DAVIS, Michael A., Jr.; US
Priority Data:
15/042,13211.02.2016US
Title (EN) MEASURING INTERNAL SIGNALS OF AN INTEGRATED CIRCUIT
(FR) SIGNAUX INTERNES DE MESURE D’UN CIRCUIT INTÉGRÉ
Abstract:
(EN) In described examples, an integrated circuit (IC) (100) includes functional logic (105) having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs (207) coupled to the plurality of internal signal lines and with an output coupled to a first external pin (102) of the IC (100). The test logic includes a buffer (223), and the test logic is configured to selectively couple (221, 222) each of the signals received on the plurality of signal lines either directly or via the buffer (223) to the first external pin (102) of the IC (100). The test logic may be configured to selectively couple a signal received on a second external pin (101) of the IC (100) via the buffer (223) to the first external pin (102) of the IC (100) in order to calibrate the buffer (223).
(FR) Dans des exemples de la présente invention, un circuit intégré (CI) (100) comprend une logique fonctionnelle (105) comportant une pluralité de lignes de signal internes et une logique d’essai. La logique de test comporte une pluralité d’entrées (207) couplées à la pluralité de lignes de signal internes et avec une sortie couplée à une première broche externe (102) du CI (100). La logique de test comprend un tampon (223), et la logique de test est configurée pour coupler sélectivement (221, 222) chacun des signaux reçus sur la pluralité de lignes de signal directement ou par l’intermédiaire du tampon (223) à la première broche externe (102) du CI (100). La logique de test peut être configurée pour coupler sélectivement un signal reçu sur une deuxième broche externe (101) du CI (100) par l’intermédiaire du tampon (223) à la première broche externe (102) du CI (100) afin d’étalonner le tampon (223).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108603914