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1. (WO2017139410) INTEGRATED DEVICE COMPRISING A CAPACITOR THAT INCLUDES MULTIPLE PINS AND AT LEAST ONE PIN THAT TRAVERSES A PLATE OF THE CAPACITOR
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Pub. No.: WO/2017/139410 International Application No.: PCT/US2017/017059
Publication Date: 17.08.2017 International Filing Date: 08.02.2017
Chapter 2 Demand Filed: 05.12.2017
IPC:
H01L 23/64 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/538 (2006.01) ,H01L 21/60 (2006.01) ,H01L 49/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Thin-film or thick-film devices
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
GU, Shiqun; US
PANDEY, Shree Krishna; US
RADOJCIC, Ratibor; US
Agent:
LOZA, Julio; US
Priority Data:
15/041,85311.02.2016US
Title (EN) INTEGRATED DEVICE COMPRISING A CAPACITOR THAT INCLUDES MULTIPLE PINS AND AT LEAST ONE PIN THAT TRAVERSES A PLATE OF THE CAPACITOR
(FR) DISPOSITIF INTÉGRÉ COMPRENANT UN CONDENSATEUR COMPORTANT DE MULTIPLES BROCHES ET AU MOINS UNE BROCHE TRAVERSANT UNE PLAQUE DU CONDENSATEUR
Abstract:
(EN) Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.
(FR) Certaines caractéristiques de l'invention se rapportent à un dispositif intégré qui comprend une puce et une première partie de redistribution couplée à la puce. La première partie de redistribution comprend au moins une couche diélectrique et un condensateur. Le condensateur comprend une première plaque, une seconde plaque, et une couche isolante située entre la première plaque et la seconde plaque. La première partie de redistribution comprend en outre plusieurs premières broches couplées à la première plaque du condensateur. La première partie de redistribution comprend en outre plusieurs secondes broches couplées à la seconde plaque du condensateur. Dans certains modes de réalisation, le condensateur comprend les premières broches et/ou les secondes broches. Dans certains modes de réalisation, au moins une broche parmi les multiples premières broches traverse la seconde plaque pour être couplée à la première plaque du condensateur. Dans certains modes de réalisation, la seconde plaque comprend une conception à ailettes.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)