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1. (WO2017138443) SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/138443 International Application No.: PCT/JP2017/003893
Publication Date: 17.08.2017 International Filing Date: 03.02.2017
IPC:
G09F 9/00 (2006.01) ,G02F 1/133 (2006.01) ,H01L 21/60 (2006.01) ,H01L 51/50 (2006.01) ,H05B 33/06 (2006.01) ,H05B 33/12 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
50
specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
02
Details
06
Electrode terminals
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
12
Light sources with substantially two-dimensional radiating surfaces
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
村上 晋三 MURAKAMI, Shinzoh; --
清水 行男 SHIMIZU, Yukio; --
堀口 武志 HORIGUCHI, Takeshi; --
Agent:
特許業務法人 安富国際特許事務所 YASUTOMI & ASSOCIATES; 大阪府大阪市淀川区宮原3丁目5番36号 5-36, Miyahara 3-chome, Yodogawa-ku, Osaka-shi, Osaka 5320003, JP
Priority Data:
2016-02391310.02.2016JP
Title (EN) SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR ET DISPOSITIF D'AFFICHAGE
(JA) 半導体装置及び表示装置
Abstract:
(EN) The present invention provides a display device in which a third bump group that prevents malfunctions due to the warpage of a semiconductor device and performs another function is provided between a first bump group and a second bump group on the semiconductor device, and in which the size of the bezel has been decreased. A semiconductor device according to the present invention comprises: a first bump group including a plurality of first bumps aligned in the long-side direction; a second bump group including a plurality of second bumps aligned in the long-side direction; and a third bump group between the first bump group and the second bump group. In at least one of the positions facing a plurality of third bumps in the short-side direction, which is perpendicular to the long-side direction, on the surface of the semiconductor device that is mounted to the display device, either no second bump is present, or at least one second bump is present and the at least one second bump is a dummy bump.
(FR) La présente invention concerne un dispositif d'affichage dans lequel un troisième groupe de bosses qui empêche des dysfonctionnements dus à la déformation d'un dispositif semi-conducteur et exécute une autre fonction est disposé entre un premier groupe de bosses et un deuxième groupe de bosses sur le dispositif semi-conducteur, et dans lequel la taille du cadre est réduite. Selon la présente invention, un dispositif semi-conducteur comprend : un premier groupe de bosses comprenant une pluralité de premières bosses alignées dans la direction du côté long ; un deuxième groupe de bosses comprenant une pluralité de deuxièmes bosses alignées dans la direction du côté long ; et un troisième groupe de bosses entre le premier groupe de bosses et le deuxième groupe de bosses. Dans au moins une des positions faisant face à une pluralité de troisièmes bosses dans la direction du côté court, qui est perpendiculaire à la direction du côté long, sur la surface du dispositif semi-conducteur qui est monté sur le dispositif d'affichage, soit aucune seconde bosse n'est présente, soit au moins une seconde bosse est présente et cette dernière est une fausse bosse.
(JA) 本発明は、半導体装置の第1バンプ群と第2バンプ群との間に、半導体装置の反りによる不具合を防止したり、その他の機能を発揮したりする第3バンプ群が配置されているとともに、狭額縁化された表示装置を提供する。本発明の半導体装置は、長辺方向に並んで配置されている複数の第1バンプを含んで構成される第1バンプ群と、長辺方向に並んで配置されている複数の第2バンプを含んで構成される第2バンプ群と、第1バンプ群と第2バンプ群との間に第3バンプ群とを備え、表示装置に実装される面内で、長辺方向に垂直な短辺方向で、複数の第3バンプの少なくとも1つと向かい合う位置に、第2バンプが配置されていないか、又は、少なくとも1つの第2バンプが配置され、該少なくとも1つの第2バンプは、ダミーバンプである。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20190041685