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1. (WO2017138197) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/138197 International Application No.: PCT/JP2016/082572
Publication Date: 17.08.2017 International Filing Date: 02.11.2016
IPC:
H01L 27/146 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/088 (2006.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
ソニー株式会社 SONY CORPORATION [JP/JP]; 東京都港区港南1丁目7番1号 1-7-1, Konan, Minato-ku, Tokyo 1080075, JP
Inventors:
富樫 秀晃 TOGASHI Hideaki; JP
中西 康輔 NAKANISHI Kosuke; JP
Agent:
山本 孝久 YAMAMOTO Takahisa; JP
吉井 正明 YOSHII Masaaki; JP
Priority Data:
2016-02271709.02.2016JP
Title (EN) SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS
(FR) DISPOSITIF À SEMI-CONDUCTEUR, PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR, ÉLÉMENT DE CAPTURE D'IMAGE À SEMI-CONDUCTEUR, ET APPAREIL ÉLECTRONIQUE
(JA) 半導体装置及び半導体装置の製造方法、並びに、固体撮像素子及び電子機器
Abstract:
(EN) Disclosed is a semiconductor device that is provided with: a semiconductor element disposed on the first surface side of a semiconductor substrate; a through electrode, which is provided by penetrating the semiconductor substrate in the thickness direction of the semiconductor substrate, and which introduces charges obtained from the semiconductor element to the second surface side of the semiconductor substrate; and an amplifier transistor that outputs electric signals based on the charges thus introduced by means of the through electrode. The amplifier transistor uses the through electrode as a gate electrode, and has a source region and a drain region around the through electrode.
(FR) L'invention concerne un dispositif à semi-conducteur comportant: un élément semi-conducteur disposé du côté d'une première surface d'un substrat semi-conducteur; une électrode traversante, qui est réalisée en pénétrant dans le substrat semi-conducteur dans le sens de l'épaisseur du substrat semi-conducteur, et qui introduit des charges obtenues à partir de l'élément semi-conducteur vers le côté de la deuxième surface du substrat semi-conducteur; et un transistor amplificateur qui délivre des signaux électriques basés sur les charges ainsi introduites au moyen de l'électrode traversante. Le transistor amplificateur utilise l'électrode traversante comme électrode de grille, et comprend une région de source et une région de drain autour de l'électrode traversante.
(JA) 本開示の半導体装置は、半導体基板の第1面側に配置された半導体素子、半導体基板を半導体基板の厚さ方向に貫通して設けられ、半導体素子で得られた電荷を半導体基板の第2面側に導く貫通電極、及び、貫通電極によって導かれた電荷に基づく電気信号を出力する増幅トランジスタを備えており、増幅トランジスタは、貫通電極をゲート電極とし、貫通電極の周りにソース領域及びドレイン領域を有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108604592KR1020180112766US20190057997