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1. (WO2017138106) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/138106 International Application No.: PCT/JP2016/053939
Publication Date: 17.08.2017 International Filing Date: 10.02.2016
IPC:
H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01) ,H04B 5/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
5
Near-field transmission systems, e.g. inductive loop type
02
using transceiver
Applicants:
ウルトラメモリ株式会社 ULTRAMEMORY INC. [JP/JP]; 東京都八王子市旭町11-8 アクセスビル3階 Access Bldg. 3F, 11-8, Asahi-cho, Hachioji-shi, Tokyo 1920083, JP
Inventors:
小川 尚記 OGAWA, Naoki; JP
上田 利次 UEDA, Toshitugu; JP
山口 和央 YAMAGUCHI, Kazuo; JP
Agent:
正林 真之 SHOBAYASHI, Masayuki; JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置
Abstract:
(EN) A semiconductor device of the present invention is provided with a plurality of memory chips laminated to each other, each of said memory chips having: a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil. The memory chips are disposed at positions where, in plan view, the first transmission/reception circuits overlap each other, and the first transmission/reception coils are disposed around the first transmission/reception circuits, said first transmission/reception coils being disposed at positions where the first transmission/reception coils do not overlap each other.
(FR) L'invention porte sur un dispositif à semi-conducteurs qui est pourvu d'une pluralité de puces de mémoire stratifiées l'une sur l'autre, chacune desdites puces de mémoire comprenant : une première bobine d'émission/réception pour une communication par couplage inductif; des premières lignes de sortie partant des deux extrémités de la première bobine d'émission/réception; un premier circuit d'émission/réception, qui est connecté aux premières lignes de sortie, qui applique des signaux à la première bobine d'émission/réception, celle-ci émettant également des signaux. Le dispositif à semi-conducteurs comprend également un élément d'interposition qui est disposé à une extrémité dans la direction de stratification des puces de mémoire, et qui possède, pour chacune des puces de mémoire : une seconde bobine d'émission/réception couplée à la première bobine d'émission/réception par couplage inductif; des secondes lignes de sortie partant des deux extrémités de la seconde bobine d'émission/réception; un second circuit d'émission/réception, qui est connecté aux secondes lignes de sortie, et qui applique des signaux à la seconde bobine d'émission/réception, celle-ci émettant également des signaux. Les puces de mémoire sont disposées à des emplacements où, en vue plane, les premiers circuits d'émission/réception se chevauchent, et les premières bobines d'émission/réception sont disposées autour des premiers circuits d'émission/réception, lesdites premières bobines d'émission/réception étant disposées à des emplacements où les premières bobines d'émission/réception ne se chevauchent pas.
(JA) 半導体装置は、誘導結合による通信用の第1の送受信コイル、第1の送受信コイルの両端から引き出された第1の引き出し線、および第1の引き出し線に接続して第1の送受信コイルとの間で信号を入出力する第1の送受信回路を各々有して積層された複数のメモリチップと、誘導結合によって第1の送受信コイルと結合する第2の送受信コイル、第2の送受信コイルの両端から引き出された第2の引き出し線、および第2の引き出し線に接続して第2の送受信コイルとの間で信号を入出力する第2の送受信回路を複数のメモリチップ毎に有して、複数のメモリチップの積層方向の一端に配置されたインターポーザとを具備する。複数のメモリチップは、平面視で、複数の第1の送受信回路が互いに重なる位置に配置され、これらの第1の送受信回路の周囲に第1の送受信コイルが互いに重ならない位置で配置される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108604586US20190035768