Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2017137682) PROCESS FOR PRODUCING CONNECTIONS TO AN ELECTRONIC CHIP
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/137682 International Application No.: PCT/FR2017/050260
Publication Date: 17.08.2017 International Filing Date: 03.02.2017
IPC:
H01L 21/768 (2006.01) ,H01L 21/32 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
32
using masks
Applicants:
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES [FR/FR]; Bâtiment Le Ponant D 25 Rue Leblanc 75015 Paris, FR
Inventors:
POSSEME, Nicolas; FR
MAZEL, Yann; FR
Agent:
CABINET BEAUMONT; 4, Place Robert Schuman B.P. 1529 38025 Grenoble Cedex 1, FR
Priority Data:
165099409.02.2016FR
Title (EN) PROCESS FOR PRODUCING CONNECTIONS TO AN ELECTRONIC CHIP
(FR) PROCEDE DE REALISATION DE CONNEXIONS D'UNE PUCE ELECTRONIQUE
Abstract:
(EN) The invention relates to a process for producing conductive connections (30) to an electronic chip, comprising the following steps: a) depositing an insulating layer (7, 9) on one face of a wafer; b) producing a layer based on at least one metal covering the insulating layer and equipped with first apertures; c) etching second apertures in the insulating layer (7, 9) in the extension of the first apertures by plasma etching in a plasma based on at least one halogen-containing compound; d) vacuum annealing the entire structure obtained after step c); and e) forming, after step d), the conductive connections in the second apertures.
(FR) L'invention concerne un procédé de réalisation de connexions conductrices (30) d'une puce électronique, comprenant les étapes suivantes : a) déposer une couche isolante (7, 9) sur une face d'une plaquette; b) réaliser une couche à base d'au moins un métal recouvrant la couche isolante et munie de premières ouvertures; c) graver des deuxièmes ouvertures dans la couche isolante (7, 9) dans le prolongement des premières ouvertures par gravure plasma à base d'au moins un composé halogéné; d) recuire sous vide l'ensemble de la structure obtenue après l'étape c); et e) former, après l'étape d), les connexions conductrices dans les deuxièmes ouvertures.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)
Also published as:
EP3414775US20190043755