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1. (WO2017137675) COMBINED INSTRUCTION FOR ADDITION AND CHECKING OF TERMINALS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/137675 International Application No.: PCT/FR2017/050107
Publication Date: 17.08.2017 International Filing Date: 19.01.2017
IPC:
G06F 9/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
UPMEM [FR/FR]; 2 Square Roger Génin 38000 Grenoble, FR
Inventors:
DEVAUX, Fabrice; FR
FURODET, David; FR
Agent:
DE JONG, Jean Jacques; FR
DE ROQUEMAUREL, Bruno; FR
MARCHAND, André; FR
Priority Data:
16 5106310.02.2016FR
Title (EN) COMBINED INSTRUCTION FOR ADDITION AND CHECKING OF TERMINALS
(FR) INSTRUCTION COMBINÉE D'ADDITION ET DE VÉRIFICATION DE BORNES
Abstract:
(EN) The invention relates to a processor core comprising, in the set of instructions thereof, a combined instruction for addition and checking of terminals (ADDCK) implicitly or explicitly defining an integer n as an instruction parameter; an adder having a width strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating a crossing signal (BX) when an addition generates a carried number of rank n.
(FR) L'invention est relative à un cœur de processeur comprenant, dans son jeu d'instructions, une instruction combinée d'addition et de vérification de bornes (ADDCK) définissant un entier n de manière implicite, ou de manière explicite comme un paramètre de l'instruction; un additionneur ayant une largeur strictement supérieure à n bits; et un circuit de traitement (MUX, 42) conçu pour répondre à l'instruction combinée par l'activation d'un signal de franchissement (BX) lorsqu'une addition génère une retenue de rang n.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)
Also published as:
CN108885548US20190050223