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1. (WO2017137635) III-NITRIDE SEMICONDUCTOR DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/137635 International Application No.: PCT/EP2017/053187
Publication Date: 17.08.2017 International Filing Date: 13.02.2017
IPC:
H01L 21/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Applicants:
HEXAGEM AB [SE/SE]; BLOMSTERGÅRDEN 15 245 62 Hjärup, SE
Inventors:
SAMUELSON, Lars; SE
OHLSSON, Jonas; SE
BI, Zhaoxia; SE
Agent:
NEIJ & LINDBERG AB; Pedellgatan 11 SE-224 60 Lund, SE
Priority Data:
16155606.312.02.2016EP
Title (EN) III-NITRIDE SEMICONDUCTOR DEVICES
(FR) DISPOSITIFS SEMI-CONDUCTEURS AU NITRURE III
Abstract:
(EN) A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first III-nitride material through a mask provided over a substrate; growing a second III-nitride semiconductor material; planarizing the grown second semiconductor material to form a plurality of discrete base elements having a substantially planar upper surface. Preferably the step of planarizing involves performing atomic distribution of III type atoms of the grown second semiconductor material under heating to form the planar upper surface, and without supply of III type atoms is carried out during the step of planarization.
(FR) L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comprenant les étapes suivantes : former une pluralité de germes de semi-conducteur en un premier matériau au nitrure III à travers un masque placé sur un substrat ; faire croître un deuxième matériau semi-conducteur au nitrure III ; planariser le deuxième matériau semi-conducteur produit pour former une pluralité d'éléments de base séparés ayant une surface supérieure sensiblement plane. De préférence, l'étape de planarisation consiste à effectuer une distribution atomique d'atomes de type III du deuxième matériau semi-conducteur produit dans des conditions de chauffage pour former la surface supérieure plane, et aucun apport d'atomes de type III n'est effectué pendant l'étape de planarisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP3414773