Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2017137248) METHOD FOR OBTAINING A GRAPHENE-BASED FET, IN PARTICULAR A MEMORY FET, EQUIPPED WITH AN EMBEDDED DIELECTRIC ELEMENT MADE BY FLUORINATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/137248 International Application No.: PCT/EP2017/051410
Publication Date: 17.08.2017 International Filing Date: 24.01.2017
IPC:
H01L 29/423 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/778 (2006.01) ,H01L 29/16 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
16
including, apart from doping materials or other impurities, only elements of the fourth group of the Periodic System in uncombined form
Applicants:
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE - CNRS [FR/FR]; 3 rue Michel Ange 75016 PARIS 16, FR
CENTRALESUPELEC [FR/FR]; 3, rue Joliot-Curie Plateau de Moulon 91192 GIF-SUR-YVETTE, FR
SORBONNE UNIVERSITE; 4, Place Jussieu 75252 PARIS Cedex 5, FR
Inventors:
BOUTCHICH, Mohammed; FR
OUERGHI, Abdelkarim; FR
LAI, Chao-Sung; TW
HO, Kuan-I; TW
Agent:
COLOMBIE, Damien; c/o Cabinet Lavoix 2, Place d'Estienne d'Orves 75441 Paris Cedex 09, FR
Priority Data:
16305161.812.02.2016EP
Title (EN) METHOD FOR OBTAINING A GRAPHENE-BASED FET, IN PARTICULAR A MEMORY FET, EQUIPPED WITH AN EMBEDDED DIELECTRIC ELEMENT MADE BY FLUORINATION
(FR) PROCÉDÉ POUR OBTENIR UN TEC À BASE DE GRAPHÈNE, EN PARTICULIER UN TEC DE MÉMOIRE, ÉQUIPÉ D'UN ÉLÉMENT DIÉLECTRIQUE NOYÉ OBTENU PAR FLUORATION
Abstract:
(EN) The invention relates to a method for obtain ing a field effect transistor, comprising steps of: - forming (100) a multi-layer graphene stack on a face of a base substrate; - depositing (200) a source and a drain electrode on the multi-layer graphene stack; - forming a conductive multi-layer graphene block by lithography and etch ing process; - fluorinating (600) the graphene block, using the source and d rain electrodes as a fluorination-protective mask, during a predetermined period and at a predetermined temperature, such that an upper part of said graphene block is converted into fluorographene over a given thickness portion, to form a dielectric element with in the graphene block; - depositing (700) a gate electrode on the dielectric element.
(FR) L'invention concerne un procédé pour obtenir un transistor à effet de champ (TEC), comprenant les étapes suivantes : - formation (100) d'un empilement de graphène multicouche sur une face d'un substrat de base; - dépôt (200) d'électrodes de source et de drain sur l'empilement de graphène multicouche; - formation d'un bloc de graphène multicouche conducteur par un processus de lithographie et de gravure; - fluoration (600) du bloc de graphène, en utilisant les électrodes de source et de drain comme masque de protection contre la fluoration, pendant une durée prédéterminée et à une température prédéterminée, de manière qu'une partie supérieure dudit bloc de graphène soit convertie en fluorographène sur une partie d'épaisseur donnée, afin de former un élément diélectrique à l'intérieur du bloc de graphène; et - dépôt d'une électrode de grille (700) sur l'élément diélectrique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20190035907